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DGNN-Booster: A Generic FPGA Accelerator Framework For�Dynamic Graph Neural Network Inference

Hanqiu Chen and Cong Hao

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Georgia Institute of Technology

School of Electrical and Computer Engineering

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Presenter: Hanqiu Chen

Email: hchen799@gatech.edu

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Sharc Lab

Code: [https://github.com/sharc-lab/DGNN-Booster]

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Dynamic Graph Neural Network

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A dynamic social network

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Dynamic Graph Neural Network

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dynamic graph modeling

A dynamic social network

A dynamic graph evolves over time

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(snapshots at different time steps)

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Different types of DGNNs

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Stacked DGNN

  • Dependent GNN and RNN in the same time step.

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  • Independent GNN at different time steps.

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Different types of DGNNs

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Stacked DGNN

  • Dependent GNN and RNN in the same time step.

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  • Independent GNN at different time steps.

Integrated DGNN

  • Dependent GNN and RNN in adjacent time step.

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  • Dependent GNN at different time steps.

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Different types of DGNNs

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Stacked DGNN

  • Dependent GNN and RNN in the same time step.

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  • Independent GNN at different time steps.

Integrated DGNN

  • Dependent GNN and RNN in adjacent time step.

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  • Dependent GNN at different time steps.

Weights-evolved DGNN

  • RNN evolves GNN weights.

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  • Independent GNN at different time steps.

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Motivations

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High energy

consumption

Low parallelism

Low GPU utilization

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[IISWC’22] Bottleneck Analysis of Dynamic Graph Neural Network Inference on CPU and GPU

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Motivations

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High energy

consumption

Low parallelism

Low GPU utilization

GNN

RNN

GNN

RNN

1

2

…

Sequential computing

GNN

RNN

GNN

RNN

Parallel computing

[IISWC’22] Bottleneck Analysis of Dynamic Graph Neural Network Inference on CPU and GPU

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Motivations

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High energy

consumption

Low parallelism

Low GPU utilization

GNN

RNN

Previous works optimize GNN or RNN separately

GNN

RNN

We optimize GNN and RNN together

GNN

RNN

GNN

RNN

1

2

3

…

Sequential computing

GNN

RNN

GNN

RNN

Parallel computing

[IISWC’22] Bottleneck Analysis of Dynamic Graph Neural Network Inference on CPU and GPU

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Innovations

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  • Better hardware performance with high flexibility
    • Lower latency and energy consumption than CPU and GPU
    • HLS allows easy integration of GNNs and RNNs

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Innovations

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  • Better hardware performance with high flexibility
    • Lower latency and energy consumption than CPU and GPU
    • HLS allows easy integration of GNNs and RNNs
  • Multi-level parallelism
    • High level: GNN and RNN in adjacent time steps are pipelined
    • Low level: Computation inside GNN and RNN is in data streaming

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Innovations

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  • Better hardware performance with high flexibility
    • Lower latency and energy consumption than CPU and GPU
    • HLS allows easy integration of GNNs and RNNs
  • Multi-level parallelism
    • High level: GNN and RNN in adjacent time steps are pipelined
    • Low level: Computation inside GNN and RNN is in data streaming
  • Hardware-efficient architecture design
    • Task scheduling, graph renumbering and different types of RAMs

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DGNN-Booster V1

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Can be applied to

Stacked DGNN

Weights-evolved DGNN

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DGNN-Booster V2

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  • Node queues: implemented using FIFOs to overlap GNN and RNN in the same time step (node-level parallelism)

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  • Message passing and node transformation in GNN are in data streaming; different stages in RNN are also in data streaming

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Can be applied to

Stacked DGNN

Integrated DGNN

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Experiment results

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End-to-end on-board evaluation

  • Dataset: BC-Alpha and UCI
  • Base model: EvolveGCN (V1) and GCRN-M2 (V2)

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  • Metric: latency, total energy and runtime energy

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Design space exploration and ablation study

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Baseline: Without applying optimizations

Pipeline-O1: Pipelines different stages inside RNN

Pipeline-O2: Overlaps GNN and RNN

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Design space exploration and ablation study

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Baseline: Without applying optimizations

Pipeline-O1: Pipelines different stages inside RNN

Pipeline-O2: Overlaps GNN and RNN

Balance GNN and RNN computation with limited DSP resource on ZCU102 board

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Future work

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  • Compare similarity between snapshots in adjacent time steps to avoid redundant data communication and computation.

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  • Automatic dynamic design configuration to balance computation resources balancing for spatial and temporal encoding parts based on the task.

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Summary & Thanks!

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Contact: hchen799@gatech.edu Sharc-lab @ Georgia Tech (https://sharclab.ece.gatech.e du/)

  • DGNNs require acceleration and real-time processing
    • Complexity of time-evolving graphs and hardware bottlenecks

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  • DGNN-Booster: our DGNN acceleration framework on FPGA
    • Generic: supports a wide range of GNN and RNN models
    • Two versions: support different dataflows
    • Open-source: High-Level Synthesis (HLS) based

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  • Beats CPU and GPU and achieve computation balance
    • Future direction1: avoid redundant computation

on similar snapshots

    • Future direction2: dynamic runtime reconfiguration

for resource and workflow balancing

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