Zero to ASIC

Democratising silicon

emBO++

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@matthewvenn

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ZeroToASICcourse.com

ZeroToASICcourse.com

Learning Aims

High level understanding of how to make a custom digital chip

Familiarity with the jargon

Approachable

Where to find help

See the tools in action for a simple design

Why

ZeroToASICcourse.com

Historical context

digital switches

How tiny switches are made into a chip

Skywater factory’s Open Source chip making specification

Digital design with a hardware description language

OpenLANE Open Source tools for chip design

Google’s free chip manufacturing opportunity

ZeroToASICcourse.com

• GCC revolutionised compiling,
• Linux revolutionised computing.
• Arduino revolutionised embedded.
• RISCV is revolutionising ISAs.
• The next step is Open Source Silicon.

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Where will this lead? Security, unpredictable innovation, simpler tools, greater accessibility, library of Open Source IP.

Why? Democratisation of Silicon

ZeroToASICcourse.com

mad, but in a good way

Niels Moseley, ASIC engineer.

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Market for semiconductors $500 BN in 2018 - pwc

1.3×10²² of the tiny switches used inside modern chips manufactured between 1960 and 2018 - Wikipedia

Smallest features sizes in 10s of nanometers - 1 x 10-9 m

m, mm, um, nm

$100k for the non returnable setup costs

ZeroToASICcourse.com

Introduction to VLSI systems 1978

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We are firm believers in learning by doing, and hope that the information provided in this chapter will help and encourage many groups of readers to try their hand at building LSI design tools and designing LSI systems.

ZeroToASICcourse.com

Digital computers need switches. Mechanisms, relays, valves, transistors.

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First transistor: 1954, Morris Tanenbaum

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First time a few were put together (IC): 1958, Kilby & Noyce

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ZeroToASICcourse.com

https://www.computerhistory.org/siliconengine/

ZeroToASICcourse.com

ZeroToASICcourse.com

https://components101.com/articles/mosfet-symbol-working-operation-types-and-applications

A MOSFET is a type of transistor we can use as a switch.

Metal Oxide Silicon Field Effect Transistor

First MOSFET: 1959, Mohamed M. Atalla & Dawon Kahng

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L = 150 nm

N type - arsenic

P type - boron

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• Easy to manufacture in volume
• Easy to change its size for speed or power
• It has become the basic building block of modern electronics

Why MOSFETS?

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NMOS Inverter

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CMOS

Complementary metal–oxide–semiconductor (CMOS) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions.

https://en.wikipedia.org/wiki/CMOS

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Low power compared to NMOS.

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Fabrication: How do you make a chip?

Draw polygons that represent where metal, SiO₂ isolation or doping/implants should exist.

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This used to be done by hand. Now we have CAD tools. You could even do this in Inkscape if you wanted to!

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A complete chip is defined by several layers of these polygons.

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Then send these layers to the chip fabricator (FAB for short). The most common way to do this is via the GDS2 file format.

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https://github.com/mattvenn/logo-to-gds2

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https://www.youtube.com/watch?v=23fTB3hG5cA

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https://en.wikipedia.org/wiki/Standard_cell

Skywater 130 standard inverter

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https://twitter.com/reivilo_t/status/1324402794783215616

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Let’s build a CMOS inverter..

https://github.com/mattvenn/magic-inverter

Demo!

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A library of all the specifications of a process used to fabricate chips.

Process Design Kit

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Google Skywater PDK standard cell library

Demo!

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https://photos.app.goo.gl/TV9q7g9eB4HCG9fF9

ZeroToASICcourse.com

ZeroToASICcourse.com

https://skywater-pdk.readthedocs.io/en/latest/rules/masks.html

33 layers

Used for building the transistors

Connecting everything up

Packaging

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Files

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DRC - antenna example

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ZeroToASICcourse.com

The Node: what does 130nm mean?

Metrics for measuring integration density were metal half-pitch and gate length. For a while they were about the same number. This number became known as the node number.

By 1990s these numbers became uncoupled, and the 130nm node actually has 70nm gates. (Skywater 130 typical minimum gate length is about 150nm).

By 2000, the node number “had by then absolutely no meaning” Paolo Gargini. IEEE article by Samuel K. Moore: The node is nonsense.

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https://www.youtube.com/watch?v=1kQUXpZpLXI

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OpenLANE https://github.com/efabless/openlane Demos done with v0.9

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15 minute install of PDK and OpenLANE docker.

Prerequisites: magic & docker

ZeroToASICcourse.com

Example: Inverter.v

ZeroToASICcourse.com

Describing circuits with a HDL

• Verilog, SystemVerilog, VHDL
• nMigen, Migen, chisel, spinal...

Y = A & B;

always @(posedge CLK)

Q <= D;

Combinatorial

Sequential

ZeroToASICcourse.com

Digital design

Clock

16MHz

Second

Counter

Digit Counter

Digit decoder

ASIC

24 bit compare

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7 segment counter in Verilog

Module definition

Setup the counters

Do the counting

Decode the counter

Demo!

ZeroToASICcourse.com

Demo!

ZeroToASICcourse.com

Most important files in the run directory

https://docs.google.com/spreadsheets/d/1YI5u9izOAu-M98WH2ftB0fTlnlqDJJyd2DKChN_Zku4/edit#gid=0&fvid=1681275274

ZeroToASICcourse.com

Demo!

ZeroToASICcourse.com

Demo!

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Demo!

ZeroToASICcourse.com

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7 segment seconds full demo

1. Create new design: ./flow.tcl -design seven_segment_seconds -init_design_config
2. Check new config.tcl
3. Copy src to src dir
4. Start openlane
5. ./flow.tcl -design seven_segment_seconds
6. Fix issues & go to 5!

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Simulation & Verification

• We are committing to physical hardware that can’t be changed
• Good idea to test things:
• Simulation - shows some functions working
• Coverage - tells you how much you have tested
• Verification - proves the validity of the design

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Google/Skywater Shuttle

ASIC

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Shuttle details

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Caravel Harness

https://caravel-harness.readthedocs.io/en/latest/?badge=latest

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Packaging: Wafer Level Chip

Scale Package

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https://github.com/efabless/caravel/blob/mpw-one-b/doc/caravel_datasheet.pdf

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Example designs and sizes

with Skywater 130nm

um²

10mm² (10e6 um²) user area, so could fit about 10 picorv32 cores inside.

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My first tapeout!

1. Seven segment seconds
2. HDMI driver
3. Frequency counter
4. TPM2137
5. WS2812 driver
6. SPI net
7. Watch
8. VGA clock
9. MUX

https://www.zerotoasiccourse.com/post/asic_submitted/

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DRC issues!

https://www.zerotoasiccourse.com/post/last_minute_drc/

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GOOGLE’s MPW-ONE

45 designs submitted

in 30 days!

60% by first time designers!

https://efabless.com/open_mpw_shuttle_project_mpw_one

https://www.zerotoasiccourse.com/interviews/

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striVe chips are in - 1st test of PDK & tools

striVe

2.743 x 2.751 mm²

Released to FAB

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Overall Timeline & Milestones

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Multi project harness v2 - extreme edition

https://github.com/mattvenn/multi_project_tools

• Improves on previous MUX solution
• Project outputs isolated with tristate buffers
• Projects are activated by the Caravel logic analyser
• Each project has 300 x 300 um
• Tools test each project and creates OpenLANE config to combine them

ZeroToASICcourse.com

The Zero to ASIC Course

• 10 hands-on projects, supported with text guides and over 6 hours of videos.
• 6 weeks support via discord server and office hours.
• Asynchronous - do in your own time.
• Next courses starting in April
• Then planned for June

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“Matt Venn's Zero To ASIC course is a real eye-opener to the possibilities of Open Source hardware. The course itself is a tour-de-force overview of almost all aspects of ASIC development from concept to GDSII. It's also great fun and regardless of your background or previous experience, you'll learn a lot and have a great deal of fun doing it. This course has inspired me to take the next step and submit my own design to efabless.” - Mike T.

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“The course is crammed full of interesting material with great pacing and support from Matt, and it's been a fantastic opportunity to meet other folks with shared interests and different backgrounds. The course has left me excited with opportunities for new projects and optimism for some working silicon!” - Jamie I.

ZeroToASICcourse.com

Thanks!

• Ahmed Ghazy
• Amr Gouhar
• Lauri Mihkels
• Kunal Ghosh
• Mohamed Shalan
• Mohamed Kassem
• Niels Moseley
• Omer Kilic
• Stuart Childs
• Ted Yapo
• Tim Mithro Ansell
• Tim Edwards
• Lots more!

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More info & next steps

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ZeroToASICcourse.com

@matthewvenn

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• Newsletter
• Course details
• Terminology list
• Interviews
• Resources - including link to these slides

ZeroToASICcourse.com