Silvia Zorzetti

Design and Engineering of Modern Beam Diagnostics, USPAS 2024

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Digital Signal Processing

The Ideal BPM Read-out Electronics!?

• Time multiplexing of the BPM electrode signals:
• Interleaving BPM electrode signals by different cable delays
• Requires only a single read-out channel!

Beam

ADC

ADC

ADC

ADC

FPGA

Fiber�Link

DAQ

PS

CLK

BPM pickup �(e.g. button, stripline)

Digital BPM electronics �(rad-hard, of course!)

Very short�coaxial cables

“Super” ADCs

“Monster” FPGA

“Ultra” low �jitter clock!

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

BPM Building Blocks

• BPM pickup
• RF device, EM field detection, �center of charge
• Symmetrically arranged electrodes, �or resonant structure
• Read-out electronics
• Analog signal conditioning
• Signal sampling (ADC)
• Digital signal processing

Analog Signal Conditioning

Digital Signal Processing

Data Acquisition

Trigger & Timing

Control

Power Supply & Misc.

BPM Pickup

position

data

control

system

(LAN)

timing,

trigger

signals

feedback bus

(if applicable)

• Data acquisition and control system interface
• Trigger, CLK & timing signals
• Provides calibration signals or other drift compensation methods

CAL

ADC

CLK

Minimize?!

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Bunched Beam BPM Signals (cont.)

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Signal Processing & Normalization

• Extract the beam position information from the electrode signals: Normalization
• Analog using Δ-Σ or 90⁰-hybrids, followed by filters, amplifiers mixers and other elements, or logarithmic amplifiers.
• Digital, performing the math on individual digitized electrode signals.
• Decimation / processing of broadband signals
• BPM data often is not required on a bunch-by-bunch basis
• Exception: Fast feedback processors
• Default: Turn-by-turn and “narrowband” beam positions
• Filters, amplifiers, mixers and demodulators in analog and digital to decimate broadband signals to the necessary level.
• Other aspects
• Generate calibration / test signals
• Correct for non-linearities of the beam position response of the BPM
• Synchronization of turn-by-turn and /or bunch-by-bunch data
• Optimization on the BPM system level to minimize cable expenses.
• BPM signals keep other very useful information�other than that based on the beam displacement, e.g.
• Beam intensity, beam phase (timing)

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Digital BPM Signal Processing

• Why digital signal processing?
• Better reproducibility of the beam position measurement
• Robust to environmental conditions, �e.g. temperature, humidity, (radiation?)
• No slow aging and/or drift effects of components
• Deterministic, no noise or statistical effects on the position information
• Flexibility
• Modification of FPGA firmware, control registers or DAQ software to adapt to different beam conditions or operation requirements
• Performance
• Often better performance, �e.g. higher resolution and stability compared to analog solutions
• No analog equivalent of digital filters and signal processing elements.
• BUT: Digital is not automatically better than analog!
• Latency of pipeline ADCs (FB applications)
• Quantization and CLK jitter effects, dynamic range & bandwidth limits
• Digital BPM solutions tend to be much more complex than some analog signal processing BPM systems
• Manpower, costs, development time, firmware / software maintenance

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Typical BPM Read-out Electronics

• Typical BPM read-out scheme
• Pipeline ADC & FPGA
• 14-16 bit, >300 MSPS, >60 dB S/N
• Separate analog signal processing for the channels

A

B

C

D

BPF

Att

A-Electrode �Analog Conditioning

B, C, D Analog same as A

Ctrl

ADC

90⁰

CIC

FIR

Σ

MEMORY

NCO

I-Channel

Q-Channel same as I

NB

WB

raw

Coordinate

Transformation

LO

CLK & Timing

A Data

• Choices:
• Analog downconverter?!
• RF locked (sync) CLK & LO signals?!
• No I-Q required

with analog downconverter

ADC

90⁰

CIC

FIR

Σ

MEMORY

NCO

I-Channel

Q-Channel same as I

NB

WB

raw

BPF

LPF

Coordinate

Transformation

CLK & Timing

A Data

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

I-Q Sampling

• Vector representation of sinusoidal signals:
• Phasor rotating counter-clockwise (pos. freq.)

Q

I

A

I

Q

φ₀

I: in-phase� component

Q: quadrature-phase� component

• I-Q sampling at:

Q(t₀)

I(t₁)

A=1.33

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Digital Down-Converter

• Goals
• Convert the band limited�RF-signal to baseband�(demodulation)
• Data reduction (decimation)
• DDC Building blocks:
• ADC
• Single fast ADC�(oversampling)
• Local oscillator
• Numerically controlled oscillator (NCO)�based on a direct digital frequency synthesizer (DDS)
• Digital mixers (“ideal” multipliers)
• Decimating low pass (anti alias) filters
• Filtering and data decimation.
• Implemented as CIC and/or FIR filters

courtesy T. Schilcher

+ϕ

+ϕ

If not synchronized

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January 28^th – February 1^st, 2019, USPAS Knoxville (TN) – Beam Position Measurements – M. Wendt

Signal analysis

IN

125MHz

14bit

Study the harmonic f0

• The FFT is possible in modern FPGA
• BUT requires high number of resources
• Complex multiplication
• Window function

ADC

Mixing

IN

125MHz

14bit

ADC

Mixing

• Mix the signal with a carrier
• Study the DC amplitude

DC

2^nd harmonic

DC

2^nd harmonic

Filtering

IN

125MHz

14bit

ADC

Mixing

• Mix the signal
• Study the DC amplitude

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Low Pass Filter LPF

• Using a low pass filter delete the second harmonic

LPF

DC

DC

2^nd harmonic

Finite Impulse Response (FIR) Filter

Analogue filter

Digital filter

Only Nominator in the impulse response

delay

Finite Impulse Response (FIR) Filter

Analogue filter

Digital filter

• Find the best trade-off between number of taps and sampling frequency
• Latency = N*ts

FIR magnitude and phase response

Filter response

• Window technique to sharp the edge of the square function

Simplified FIR

Even number of taps

• N/2 coefficients

Odd number of taps

N/2+1 coefficients

IIR filter

Filter Design - Matlab

Filter coefficients in FPGA

• Store the coefficients in FPGA
• Same error as the ADC
• Coefficients resolution from number of bits

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​

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• The output of a mixer is N+M in bit length

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• If N=16, M=16
• Mixer output =32
• Take the most significant after the operation

M bit

IN

N bit

N+M bit

FIR design

IN

125MHz

14bit

ADC

LPF

DC

FIR design

IN

125MHz

14bit

ADC

LPF

DC

Simplify

Downsampling (1)

• Zero Order Hold (ZOH)

Rectangular signal

Sinc in frequency

unwanted harmonics

Rect in time

Sinc in frequency

Downsampling (1)

• Zero Order Hold (ZOH)

Rectangular signal

Sinc in frequency

If the signal has multiple harmonics, the spectrum is distorted

unwanted harmonics

Downsampling (2)

CIC filter design

CIC magnitude response

Anti Aliasing band

Notch

CIC Filtering

IN

125MHz

14bit

ADC

CIC

DC

FPGA IP may be limited

CIC Filtering

IN

125MHz

14bit

ADC

CIC

DC

CIC

R=125, M=2

CIC

R=250, M=2

2kHz notch

CIC Filter implementation with MATLAB

CIC

R=176, N=2, M=2

CIC

R=176, N=2, M=2

2kHz notch

Low pass filtering

IN

125MHz

14bit

ADC

CIC

DC

FIR

FIR filter implementation with MATLAB

Digital Downconverter

CIC

CIC

FIR

FIR

NCO

ADC

Magnitude

^2

^2

Phase

cordic

Numerical Controlled Oscillator

Exercise

CIC

CIC

FIR

FIR

NCO

ADC

Sketch the spectrum of the signals step by step

Design

• NCO
• CIC
• FIR

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• Calculate the bit numbers