Corundum status updates

Alex Forencich

3/14/2022

Mailing list, slack, and survey: https://join.corundum.io/

Agenda

• Status updates

Mailing list, slack, and survey: https://join.corundum.io/

Status update summary

• Documentation (initial version done)
• Variable-length descriptor support (todo)
• RX queue selection logic (todo)
• Management soft core (todo)
• PHY status registers (todo)
• GTY/PLL DRP (done)
• 10G/25G switching (HW done, SW todo)

Mailing list, slack, and survey: https://join.corundum.io/

Documentation

• Use sphinx for documentation
• Imported content from readme and wiki
• Added register block documentation
• Module documentation partially done
• Status: Initial version done

Variable-length descriptor support

• Current queue management logic does not handle variable-length descriptors
• Implement simplified queue managers (state storage only)
• Implement descriptor fetch and header parsing logic
• Read descriptors in blocks up to some block size, parse length/type fields and hand off to transmit/receive engines
• Potential extensions to support LSO (descriptor duplication)
• Initial step: use descriptor headers and new queue pointer logic, with old descriptor fetch logic
• Status: initial implementation

RX queue selection logic

• Combine tid, tdest, and RSS hash to determine RX queue
• SW should have ultimate control over which set of queues are used
• app_mask, rss_mask, offset are per-tid (source port)
• Queue = (tdest & app_mask) + (rss_hash & rss_mask) + offset
• Status: TODO

Management soft core

• Soft core for board-level management
• Handle board and device specific functions
• Present unified interface to driver
• Location: board-level or inside core?
• API
• Low-level – direct register access, etc. Board-dependent diagnostics
• Medium-level – Somewhat abstracted operations
• High-level – High-level operations, board and FPGA independent
• Core: probably vexriscv
• JTAG debug interface, can simulate with icarus verilog
• Status: core bring-up

PHY status registers

• Implement status registers
• Expose overview of link state and capabilities
• Block lock, AN status, LOS, current and supported speeds, etc.
• Control and more complex status handled via soft core
• Status: TODO

GTY/PLL DRP

• Connect transceiver and PLL DRP interfaces to soft core
• FPGA-specific diagnostics
• Parameter tuning (EQ, emphasis, swing, etc.)
• Low-level link status monitoring
• Eye Scan
• Soft core provides bridge
• Several API levels (low/medium/high)
• Low/medium level are device-dependent, used by userspace tools
• Driver uses high-level device-independent API only
• Soft core performs arbitration, waits for resets, etc.
• Status: Done, all designs updated

​

10G/25G switching

• Run-time switching between 10G and 25G should be doable
• Change speeds and mix and match speeds without reloading FPGA
• Run two QPLLs, dynamically switch channel clock sources
• Possibly can also switch EQ settings (DFE vs LPM)
• Requires resetting both RX and TX
• Previously blocked on FIFO reset rework and PHY integration updates
• Status: Working from userspace, need to move to softcore FW
• TODO: update transmit engine to handle dropped TX packets when PTP is enabled

To-do list for stable release

• Application section [done]
• Register space reorganization [done]
• Shared interface datapath [initial version done]
• Self-contained checksum offloading (no checksum in desc)
• Variable-length descriptor support
• On-FPGA management soft core (no board-specific kernel code)
• Overall goal: stabilize driver/hardware interface