CP 302 Capstone Project
Presentation on
Submitted To: Dr. Ashwani Sharma (Project Supervisor)
Dr. Hande V. Gopal (Course Instructor)
Presented By: Ajey Singh Bhadauria (2018eeb1133)
Design of Patch Antenna Array for 5G applications
Introduction
Low profile and cost, easy to fabricate, integratable with feed networks on a single substrate
Narrow Bandwidth (major disadvantage), low radiation efficiency
Introduction to Patch Antenna
Patch Antenna Element Design and Results
FR4 Substrate (Relative Permittivity = 4.4) | Thickness = 1.6mm |
Quarter Wave Transformer (Z0 = 110.22 ohms ) | Width = 0.53mm, Length = 7.49mm |
Patch (Designed for f = 5.8GHz) | Width = 15.739 mm, Length = 11.75mm |
Design
Need to improve Impedance Bandwidth and Peak Gain !
Planar Array design (with straight connecting feedlines)
Feedline connected to source | W = 3.058 mm | L = 7.085 mm |
Corporate feedline | W = 0.71 mm | L = 51.72 mm |
QWT | W = 0.152 mm | L = 7.085mm |
Connecting lines | W = 0.71 mm | L = 12.33 mm |
Patch Antenna | W = 15.739 mm | L = 11.75 mm |
Results
There is significant increase in peak gain of the system and the sidelobes have quite less gain in comparison to the major lobe. The radiation efficiency is low due to feedline losses in the corporate feedline configuration.
Results (after Parametric Sweeps)
Orange trace indicates return loss plot after all optimisations.
S21 plot (in dB)
Planar Array design (with U-shaped connecting feedlines)
Results
Conclusion
We have successfully designed a high gain(~7.44), linearly polarized Planar patch antenna array having a large impedance bandwidth (~12%) with resonant dip around 5.35GHz and 5.75GHz.
Thanks for listening patiently !