Holdover Challenges in NIC Based Boundary Clocks
Eyal Cohen, Silicom, eyalc@silicom.co.il, July 2021
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Storyboard
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Acknowledgements
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What is it that we promote
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Section 1�Timing Synch’ NIC
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What are the pieces
PCIe Gen4 x16
STS2
PCIe form factor
Full Height, Half Length, Single Slot
BMC
SFP+
SFP+
SFP+
SFP+
PTP/1588
SyncE
QSFP+
GNSS
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What are the pieces (cont.)
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Where does it operate, Baseband Nodes
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What are the challenges
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What are the challenges
Baseband Node
NIC, master ports
NIC master ports
NIC, slave ports
To Backhaul
To Fronthaul
1588
SyncE
G.8275.1
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What a holdover is
Once two independent clocks are synchronized, they will start walking and straying away from one another
Quality of oscillator affects holdover performance
Holdover is important for business continuity
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Section 2�Selected Holdover Issues
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Problem Statement
| SyncE | PTP | Required Behavior | Governing standard |
| A | B | C | D |
1 | Down | Up | ? | n/a |
2 | Up | Down | No holdover to PLL; Yes holdover to physical layer frequency, SyncE, whilst QL is ok (Class A, B); Class (D, C) for further study | G.8273.2 |
3 | Down | Down | ? | Sec. 7.4.2.1 in G.8273.2, for further study |
4 | Up | Up | Full timing support (FTS) | G.8271.1 |
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SyncE Up, PTP Down
| SyncE | PTP | Required Behavior | Governing standard |
| A | B | C | D |
2 | UP | Down | No holdover to PLL; Yes holdover to physical layer frequency, SyncE, whilst QL is ok (Class A, B); Class (C, D) for further study | G.8273.2 (table below) |
MTIE limits [ns] | Observation Interval τ [s] |
| 1 <= τ <= 100 |
| 100 <= τ <= 1000 |
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SyncE Down, PTP Up
| SyncE | PTP | Required Behavior | Governing standard |
| A | B | C | D |
1 | Down | Up | ? | n/a |
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SyncE Down, PTP Down
| SyncE | PTP | Required Behavior | Governing standard |
| A | B | C | D |
3 | Down | Down | ? | n/a |
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For Further Study
| SyncE | PTP |
1 | Down | Up |
2 | Up | Down |
3 | Down | Down |
4 | Up | Up |
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THANK YOU
www.silicom-usa.com
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Backup
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Who Are We?
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A public company NASDAQ
HQ, R&D and manufacturing facilities are in Israel, with offices in the US and Denmark
33 years of experience in networking and connectivity
300 employees
Collaboration with strategic partners
Over 300 clients worldwide
FPGA design experts both HW and IP cores
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