ARM Cortex-M3

Features • Architecture • Programmer’s Model • Special Registers�Operating Modes & States • MPU • Memory Map • NVIC

University of Mumbai syllabus – Module 2.2

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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Cortex-M3: Big Picture

FEATURES

ARM Cortex-M3�32-bit MCU Core

Thumb-2

3-stage�pipeline

Programmer’s�model

NVIC +�exceptions

MPU

Memory map

Core idea: CPU + registers + memory system + interrupt controller work together to run embedded applications.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

2

Cortex-M3 Architecture

ARCHITECTURE

Cortex-M3 CPU

Register�File

ALU +�Control

3-stage�Pipeline

NVIC

I-Code Bus

D-Code Bus

System Bus

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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Pipeline & Bus Interfaces

ARCHITECTURE

FETCH

Read instruction

DECODE

Interpret instruction

EXECUTE

ALU/control operation

CPU Core

I-Code�Instruction

D-Code�Data/Literal

System Bus�SRAM/Peripheral

PPB�Core peripherals

internal bus structure improves throughput; peripherals are accessed through memory-mapped addresses.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

4

Programmer’s Model – Registers

PROGRAMMER’S MODEL

R0–R12

General-purpose

R13 = SP

Stack Pointer

R14 = LR

Link Register

R15 = PC

Program Counter

xPSR

Program Status

What students should remember

• R0–R12: data, addresses, temporary values

• SP: points to the current stack

• LR: holds return information

• PC: controls instruction flow

• xPSR: flags + execution status + exception number

32-bit registers + Thumb / Thumb-2 instruction execution

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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Special Registers & xPSR

SPECIAL REGISTERS

xPSR

APSR�N Z C V

IPSR�Exception No.

EPSR�Execution state

PRIMASK

Mask configurable interrupts

FAULTMASK

Mask exceptions except NMI

BASEPRI

Priority threshold masking

CONTROL

Privilege + stack selection

Exam focus: PRIMASK ≠ FAULTMASK ≠ BASEPRI; CONTROL selects privilege and Thread-mode stack.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

6

Operating Modes, States & Privilege

MODES & STATES

Cortex-M3

Thread Mode

Handler Mode

Privileged

Unprivileged

Always�Privileged

Thumb State

Debug State

Thread = normal application execution; Handler = exception/interrupt execution. Handler mode is always privileged.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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Stacking & Exception Entry

EXCEPTIONS

1

Interrupt / exception occurs

2

CPU accepts it

3

Registers are stacked

4

Handler mode entered

5

Vector table gives ISR address

6

ISR executes → exception return

Hardware stacking is one reason Cortex-M3 can respond to interrupts quickly and return to the interrupted program efficiently.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

8

Memory Map – 4 GB Address Space

MEMORY MAP

0x0000_0000�Code

Flash / program

0x2000_0000�SRAM

Stack, variables, data

0x4000_0000�Peripherals

GPIO, timers, UART etc.

0x6000_0000�External RAM

External memory

0xA000_0000�External Device

External devices

0xE000_0000�PPB

NVIC, SCB, SysTick

32-bit address bus → 2³² = 4 GB addressable space

Memory-mapped I/O

Peripherals appear at addresses; CPU accesses them using load/store operations.

Bit-banding�selected SRAM + peripheral regions

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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MPU – Memory Protection Unit

MPU

CPU Access

MPU�Access Check

Allowed

Fault

Region 0�Code

Region 1�SRAM

Region 2�Peripheral

Permissions�R / W / X

Purpose: prevent unintended access and support safer separation of application and system resources.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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NVIC – Nested Vectored Interrupt Controller

NVIC

Interrupt Sources

GPIO

Timer

UART

ADC

NVIC

Enable�Pending�Priority�Active

CPU / ISR

Nested = higher-priority interrupt can pre-empt a lower-priority ISR.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

11

Vector Table & Interrupt Flow

NVIC

Vector Table

Initial MSP

Reset Handler

System Exceptions

External IRQ Handlers

Handler Address

ISR

Return

At reset, entry 0 provides the initial stack pointer and entry 1 points to the Reset Handler.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

12

How All Topics Connect – One Example

INTEGRATION

Sensor / Button

GPIO / Timer

NVIC

Cortex-M3 CPU

ISR

Programmer’s Model�SP • LR • PC • xPSR

Memory Map�Code • SRAM • Peripherals

MPU�Access protection

Teaching message: the CPU executes code, registers hold context, memory stores code/data, MPU checks access, and NVIC manages events.

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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MU Exam-Oriented Diagram Questions

EXAM FOCUS

1

Draw & explain Cortex-M3 architecture

2

Draw programmer’s model and explain registers

3

Explain special registers + operating modes/states

4

Draw 4 GB memory map and explain MPU

5

Draw NVIC + vector table + interrupt flow

High-value exam diagrams: Architecture • Programmer’s Model • Memory Map • MPU • NVIC/Vector Table

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

14

One-Slide Revision

RECAP

Features

32-bit • Thumb-2 • pipeline • fast interrupts

Architecture

CPU • buses • NVIC • debug

Registers

R0–R12 • SP • LR • PC • xPSR

Modes

Thread / Handler • privilege

MPU

Regions • permissions • fault

Memory

4 GB map • memory-mapped I/O • bit-band

NVIC

Enable • pending • priority • nesting

Core teaching sequence: Architecture → Registers → Modes → Memory/MPU → NVIC → Integrated example

ARM Cortex-M3 • Embedded Systems & RTOS • MU Exam-Oriented

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