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Flip Flops�

Dr. R. Murugesan

Associate Professor of Computer Science

C.P.A. College

Bodinayakanur

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Introduction

  • A sequential circuit consists of a feedback path, and employs some memory elements.

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Combinational logic

Memory elements

Combinational outputs

Memory outputs

External inputs

Sequential circuit = Combinational logic + Memory Elements

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Introduction

  • There are two types of sequential circuits:
    • synchronous: outputs change only at specific time
    • asynchronous: outputs change at any time
  • Multivibrator: a class of sequential circuits. They can be:
    • bistable (2 stable states)
    • monostable or one-shot (1 stable state)
    • astable (no stable state)
  • Bistable logic devices: latches and flip-flops.
  • Latches and flip-flops differ in the method used for changing their state.

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Memory Elements

  • Memory element: a device which can remember value indefinitely, or change value on command from its inputs.
  • Characteristic table:

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command

Memory element

stored value

Q

Q(t): current state

Q(t+1) or Q+: next state

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Memory Elements

  • Memory element with clock. Flip-flops are memory elements that change state on clock signals.
  • Clock is usually a square wave.

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command

Memory element

stored value

Q

clock

Positive edges

Negative edges

Positive pulses

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Memory Elements

  • Two types of triggering/activation:
    • pulse-triggered
    • edge-triggered
  • Pulse-triggered
    • latches
    • ON = 1, OFF = 0
  • Edge-triggered
    • flip-flops
    • positive edge-triggered (ON = from 0 to 1; OFF = other time)
    • negative edge-triggered (ON = from 1 to 0; OFF = other time)

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S-R Latch

  • Complementary outputs: Q and Q'.
  • When Q is HIGH, the latch is in SET state.
  • When Q is LOW, the latch is in RESET state.
  • For active-HIGH input S-R latch (also known as NOR gate latch),

R=HIGH (and S=LOW) 🢧 RESET state

S=HIGH (and R=LOW) 🢧 SET state

both inputs LOW 🢧 no change

both inputs HIGH 🢧 Q and Q' both LOW (invalid)!

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S-R Latch

  • Characteristics table for active-high input S-R latch:

​

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S

​

R

Q

​

Q'

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S-R Latch

  • Active-HIGH input S-R latch

​

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R

S

Q

Q'

0

1

1

0

0

0

1

0

1

0

0

1

0

0

0

1

1

1

0

0

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Gated D Latch

  • Make R input equal to S' → gated D latch.
  • D latch eliminates the undesirable condition of invalid state in the S-R latch.

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D

EN

Q

​

Q'

D

Q

Q'

EN

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Gated D Latch

  • When EN is HIGH,
    • D=HIGH → latch is SET
    • D=LOW → latch is RESET
  • Hence when EN is HIGH, Q ‘follows’ the D (data) input.
  • Characteristic table:

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When EN=1, Q(t+1) = D

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Latch Circuits: Not Suitable

  • Latch circuits are not suitable in synchronous logic circuits.
  • When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.
  • The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.
  • This leads us to the edge-triggered memory elements called flip-flops.

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Edge-Triggered Flip-flops

  • Flip-flops: synchronous bistable devices
  • Output changes state at a specified point on a triggering input called the clock.
  • Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.

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Positive edges

Negative edges

Clock signal

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Edge-Triggered Flip-flops

  • S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input.

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S

C

R

Q

​

Q'

S

C

R

Q

​

Q'

D

C

Q

​

Q'

D

C

Q

​

Q'

J

C

K

Q

​

Q'

J

C

K

Q

​

Q'

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops

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S-R Flip-flop

  • S-R flip-flop: on the triggering edge of the clock pulse,
    • S=HIGH (and R=LOW) 🢧 SET state
    • R=HIGH (and S=LOW) 🢧 RESET state
    • both inputs LOW 🢧 no change
    • both inputs HIGH 🢧 invalid
  • Characteristic table of positive edge-triggered S-R flip-flop:

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X = irrelevant (“don’t care”)

↑ = clock transition LOW to HIGH

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S-R Flip-flop

  • It comprises 3 parts:
    • a basic NAND latch
    • a pulse-steering circuit
    • a pulse transition detector (or edge detector) circuit
  • The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.

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S-R Flip-flop

The pulse transition detector.

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S

Q

Q'

CLK

Pulse transition detector

R

Positive-going transition

(rising edge)

CLK

CLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition

(falling edge)

CLK'

CLK

CLK*

CLK

CLK'

CLK*

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D Flip-flop

  • D flip-flop: single input D (data)
    • D=HIGH 🢧 SET state
    • D=LOW 🢧 RESET state
  • Q follows D at the clock edge.
  • Convert S-R flip-flop into a D flip-flop: add an inverter.

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A positive edge-triggered D flip-flop formed with an S-R flip-flop.

S

C

R

Q

​

Q'

CLK

D

↑ = clock transition LOW to HIGH

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J-K Flip-flop

  • J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
  • No invalid state.
  • Include a toggle state.
    • J=HIGH (and K=LOW) 🢧 SET state
    • K=HIGH (and J=LOW) 🢧 RESET state
    • both inputs LOW 🢧 no change
    • both inputs HIGH 🢧 toggle

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J-K Flip-flop

  • J-K flip-flop.
  • Characteristic table.

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J

Q

Q'

CLK

Pulse transition detector

K

Q(t+1) = J.Q' + K'.Q

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T Flip-flop

  • T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.
  • Characteristic table.

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Q(t+1) = T.Q' + T'.Q

T

Q

Q'

CLK

Pulse transition detector

J

C

K

Q

​

Q'

CLK

T

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Thank You