CSC/EEE120�Class Project / Demo��Stepper Motor Control�using VHDL�

State Diagram

S0

Output: 0001

​

S2

Output: 0010

​

S1

Output:0100

S3

Output: 1000

A=0

A = 1

A=1

A=1

A=0

A=0

Input: A

Output: M3 M2 M1 M0

A=1

A=0

I/O Assignments

entity FSM is

Port (

CLK: in STD_LOGIC;

-- Inputs --

SW3 : in STD_LOGIC; -- C (not used)

SW2 : in STD_LOGIC; -- B (not used)

SW1 : in STD_LOGIC; -- A (Direction Control)

SW0 : in STD_LOGIC; -- Reset

--Outputs --

LD7 : out STD_LOGIC;

LD6 : out STD_LOGIC;

LD5 : out STD_LOGIC;

LD4 : out STD_LOGIC;

LD3 : out STD_LOGIC;

LD2 : out STD_LOGIC;

LD1 : out STD_LOGIC;

LD0 : out STD_LOGIC;

M3 : out STD_LOGIC; -- JA connector signals to control Stepper motor

M2 : out STD_LOGIC;

M1 : out STD_LOGIC;

M0 : out STD_LOGIC;

-- For Testing/Visual Feedback Only --

RUN_TIMER: out STD_LOGIC

);

end FSM;

Signal Declarations

architecture Behavioral of FSM is

​

type STATE is (S0,S1,S2,S3);

signal CURR_STATE,NEXT_STATE: STATE;

​

signal Reset,A,B,C: STD_LOGIC;

​

signal REG : std_logic_vector(27 downto 0) := (others => '0');

signal CLK_DIV_INT :STD_LOGIC;

signal Q_INT: std_logic_vector(3 downto 0);

​

begin --Behavioral

​

Reset <= SW0;

A <= SW1; -- direction control

B <= SW2; -- not used

C <= SW3; -- not used

​

LD0 <= Reset;

LD1 <= A; -- direction control indicator

LD2 <= B; -- not used

LD3 <= C; -- not used

CLK process

process (CLK,REG) begin

​

if rising_edge(CLK) then

REG <= REG + 1; CLK_DIV_INT<='0';

end if;

if REG = X"2FAF080" then -- For 1 Hz use X"2FAF080" = 50,000,000 (Decimal)

-- 50 MHz / 50,000,000 = 1 Hz

CLK_DIV_INT<='1';

REG<=X"0000000";

end if;

end process;

SYNC process

SYNC: process (CLK_DIV_INT,Reset)

Begin

​

if Reset = '1' then

CURR_STATE <= S0;

​

elsif rising_edge (CLK_DIV_INT) then

CURR_STATE <= NEXT_STATE;

end if;

​

end process SYNC;

STATE_MACHINE process� state S0

STATE_MACHINE: process (CURR_STATE,Reset,A)

begin

​

case (CURR_STATE) is

when S0 =>

if A = '1' then

NEXT_STATE <= S3;

else NEXT_STATE <= S1;

end if;

-- Output:

LD4 <= '1';

LD5 <= '0';

LD6 <= '0';

LD7 <= '0';

-- To JA connector signals to drive stepper motor:

M0 <= '1';

M1 <= '0';

M2 <= '0';

M3 <= '0';

STATE_MACHINE process� state S1

when S1 =>

if A = '1' then

NEXT_STATE <= S0;

else NEXT_STATE <= S2;

end if;

​

-- Output indicators:

LD4 <= '0';

LD5 <= '0';

LD6 <= '1';

LD7 <= '0';

-- To JA connector signals to drive stepper motor

M0 <= '0';

M1 <= '0';

M2 <= '1';

M3 <= '0';

STATE_MACHINE process� state S2

when S2 =>

if A = '1' then

NEXT_STATE <= S1;

else NEXT_STATE <= S3;

end if;

-- Output:

LD4 <= '0';

LD5 <= '1';

LD6 <= '0';

LD7 <= '0';

​

-- To JA connector signals to drive stepper motor

M0 <= '0';

M1 <= '1';

M2 <= '0';

M3 <= '0';

STATE_MACHINE process� state S3

when S3 =>

if A = '1' then

NEXT_STATE <= S2;

else NEXT_STATE <= S0;

end if;

-- Output:

LD4 <= '0';

LD5 <= '0';

LD6 <= '0';

LD7 <= '1';

​

-- To JA connector signals to drive stepper motor:

M0 <= '0';

M1 <= '0';

M2 <= '0';

M3 <= '1';

end case;

​

end process STATE_MACHINE;

Demonstrate VHDL Running Stepper motor