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RISC-Q: A Generator for Real-time Quantum Control System-on-Chip (SoCs) compatible with RISC-V

Xiaodi Wu

Joint work with Junyi Liu, Yi Lee, Haowei Deng, Connor Clayton, and Gengzhi Yang

arXiv: 2505.14902 DAC 2026

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Department of Computer Science

Joint Center for Quantum Information and Computer Science

University of Maryland, College Park

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Real-time Control in Quantum Computing

Quantum System

Calibration

Reconfiguration

Dynamic Circuit

Error Correction

…

Digital Controller

Control

Pulse

Readout

Signal

Quantum Controller

Feedback Control

ASAP

Network

Multi-chip

Microwave

Laser/Camera

QPU-GPU/FPGA

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Real-time Control in Quantum Computing

Quantum System

Error Correction

Quantum Controller

1. Measurement Pulse

2. Readout Signal

3. Error Syndrome

4. Correcting Pulse

ASAP

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Real-time Control in Quantum Computing

Superconducting System

Quantum Controller

Control

Pulse

Readout

Signal

ns~us

​

1 qubit

8 GHz

14 bits

112 Gbps

~5 GHz

 

 

 

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Real-time Requirements from Physics

  • High frequency: ~GHz
  • Precise timing: jitter << 1 ns
  • Low-latency feedback: < 1 us
  • Only customized hardware can do

Superconducting System

Quantum Controller

Control

Pulse

Readout

Signal

ns~us

​

1 qubit

8 GHz

14 bits

112 Gbps

5 GHz

 

QubiC

QICK

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Overview of Quantum Software Stack

Application

Program

Qiskit, Bracket, Cirq, Qibo, …

Hardware

Primitive

Fault-tolerant:

Circuit

NISQ:

Hamiltonian

Control

Instruction

Classical Instructions:

Arithmetic, Branch, Load/Store, …

Quantum Instructions:

Pulse, Readout, Error Correction, …

 

 

 

Superconducting System

Analog

Signal

Voltage, Current, …

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Complexity in building such control systems

  • Although emerging quantum systems are not powerful yet enough to deliver practical quantum advantages, they are complicated enough to control
  • We are at the dawn of investigating quantum control systems without knowledge of their ultimate shapes. We need to build and research many such control systems.
  • Existing workflow (e.g., Verilog-based) is labor-intensive and expensive for fast prototyping.

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Our Vision

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Real-time requirements

  • RFSoC: Radio Frequency System-on-Chip
  • Carefully designed hardware controller on RFSoC can meet the requirements
  • However, hardware design is complicated…

Xilinx RFSoC

QubiC

QICK

FPGA Quantum Controller on RFSoC

ARM

Processor

FPGA

Chip

DAC/ADC

~$16,000 for 16 DACs and 16 ADCs

~$1,000 for controlling a qubit

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Real-time Control in Quantum Computing

Superconducting System

Quantum Controller

Control

Pulse

Readout

Signal

<1 us

​

1 qubit

8 GHz

14 bits

112 Gbps

5 GHz

 

RISC-Q:

Open-source

High-level

Design Tool

for Fast prototyping

Quantum Controller

 

 

Goals:

  • Better productivity inbuilding complex controllers
  • Lower the cost/barrier to enable agile prototyping
  • A platform to build an ecosystem like RISC-V

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Architecture of QC-SoC by RISC-Q

  • Overview of Quantum Control System-on-Chip (QC-SoC) generated by RISC-Q

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Architecture of QC-SoC by RISC-Q

  • Basic setting for Superconducting Circuit

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Architecture of QC-SoC by RISC-Q

  • RISC-V controller

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Architecture of QC-SoC by RISC-Q

  • Trapped Ion and Neutral Atom systems

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  • Hardware Accelerators

Architecture of QC-SoC by RISC-Q

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Architecture of QC-SoC by RISC-Q

  • Distributed Architecture for Scaling

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Why a High-level Tool?

  • Hardware Customizability
    • Different experiments need different hardware designs
    • Different functions: RF signal generator, decoder, accelerator, …
    • Different parameters: frequency, latency, throughput, power, area, …
    • ...
  • We need a fast-prototyping platform to explore the huge design space

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Decoder

1

Signal

Generator

1

Controller

1

Controller

2

Controller

3

Decoder

2

Decoder

3

Signal

Generator

2

Signal

Generator

3

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Linux as an example

  • Collaborate on an extensible ecosystem
    • Linux kernel, GNU compiler, GNU C Library, …
    • Save the manpower
  • Configurable & Composable modules for specific requirements
    • File systems, Drivers, Libraries, Applications…
    • Design on high-level abstraction of hardware
    • Configurability & Modularity
    • Fast prototyping
    • Collaborative and Iterative development

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Ideal Ecosystem for Shared Innovation

Alice

Bob

I build a new Decoder!

I build a new Signal Generator!

Great! Let me try the combination!

Charlie

Decoder

Signal

Generator

Controller

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High-level HDL

  • QubiC & QICK are written in Verilog & VHDL
    • Verilog & VHDL are low-level HDLs
    • Manually write down every wires, registers

and connections in the circuit

  • SpinalHDL is a high-level HDL
    • Instead of writing a circuit,

write a program that generate the circuit

    • Fast prototyping
    • Parameterization

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Approach taken by, e.g., QubiC, QICK, Artiq, or so..

RISC-Q approach with modeling the general QCSoC

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RISC-Q-Core

Development Efficiency:

  • RISC-Q enables highly configurable implementation
  • Code-base: 25% of Qubic, <10% of QICK

Implementation Efficiency:

  • Latest RISC-Q-Core allows 30 DDS in one ZCU216; 500 MHz w/ 16 DACs & ADCs
  • 14 qubit w/ one RFSoC board

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Programming Interface, Software & Hardware Stack for QC SoC generated by RISC-Q

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Architecture of QC-SoC by RISC-Q

  • RISC-V controller

Quantum Program ( OQASM 3)

RF Signal Processing Program

(Written in C, MM-I/O approach)

RISC-V Instructions

Compiler

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Measures on Prototype built with 3 RFSoC AMD ZCU216 w/ additional classical electronics from QubiC

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Architecture of QC-SoC by RISC-Q

  • Example: On-chip Calibration

Calibration by frequency sweeping

(Written in C)

✓

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A Scalable Open-Source RISC-V-Based Quantum Error Correction System with Sub-Microsecond Decoding Latency

(arXiv: 2603.16203)

Junyi Liu1, Yi Lee1, Yilun Xu2, Gang Huang2, and Xiaodi Wu1

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1Department of Computer Science, Joint Center for Quantum Information and Computer Science, University of Maryland, College Park

2Lawrence Berkeley National Laboratory, Berkeley, CA

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Desiderata for a real-time QEC

  • Active studies on hardware decoders, controllers
  • A holistic design will be critical for the overall performance

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🡨 this work

Key Insights: a holistic design for an integrated performant system based on RISC-Q -- an open-source RISC-V Quantum Control System-on-Chip (QCSoC) generator.

Junyi Liu, Yi Lee, Haowei Deng, Connor Clayton, Gengzhi Yang, and Xiaodi Wu, DAC 2026

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Desiderata for a real-time QEC

  • Low Latency
    • Fast feedback for logical operation
  • Scalability
    • Support ~1000 qubits

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2-3 DAC Channels / Qubit

16 DAC Channels / RFSoC

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Distributed QEC Architecture

  • Multi-Core
    • Dedicated core for each qubit maximizing gate throughput
  • Multi-Board
    • Scaling by simply adding more boards (nodes)
  • Fully hardware feedback loop
    • Minimize the feedback latency

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Scaling Challenges

  • Low latency communication
    • ~ 150 ns one-way latency with custom protocol
  • High-precision synchronization
    • < 1 ns timing difference between nodes with Precision Time Protocol (PTP)

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Fast QEC Decoding

  • Fully hardware decoder Helios
    • Union-find decoder
    • < 250 ns latency for distance 21

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Evaluation

  • Prototype with 3 ZCU216 RFSoCs
    • Loopback emulated readout signal to simulate syndrome measurement
    • Implemented with 14k LOCs in RISC-Q, 1.5k LOCs in Python and C

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Performance

  • Decoding-feedback latency 446 ns for distance-3 surface code

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Performance

  • Achieving an order of magnitude better than SOTA through
    • Fully hardware pipeline
    • Tight integration of components

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Extrapolated Performance

  • Extrapolates with the performance of the Helios decoder and the measured communication latency
  • The sharp increase in latency between code distances 15 and 17 arises from the introduction of router layer for further scaling
  • Expect sub-microsecond latency for distance-21 surface code with 881 qubits

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Scaling Challenges

  • Low latency communication
    • ~ 150 ns one-way latency with custom protocol1
  • High-precision synchronization
    • < 0.2 ns timing offset between nodes with Precision Time Protocol (PTP)

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1Liyanage, Namitha, et al. "Network-integrated decoding system for real-time quantum error correction with lattice surgery." 2025 IEEE International Conference on Quantum Computing and Engineering (QCE). Vol. 1. IEEE, 2025. github.com/yale-paragon/EosCore

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Fast QEC Decoding

  • Fully hardware decoder Helios1
    • Union-find decoder
    • < 250 ns latency for distance 21 at 0.001 physical error rate
  • Modular design
    • Alternative decoders easily fit in

1Liyanage, Namitha, et al. "FPGA-based distributed union-find decoder for surface codes." IEEE Transactions on Quantum Engineering 5 (2024): 1-18.

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Evaluation

  • Prototype with 3 ZCU216 RFSoCs in the QubiC hardware system
    • Loopback emulated readout signal to simulate syndrome measurement

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Performance

  • Decoding-feedback latency 446 ns for distance-3 surface code

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Comparing with other approach

  • The performance is achieved through
    • Low-latency communication
    • Low-latency decoding
    • Low-overhead hardware integration

Google: Google Quantum AI (2025). Quantum error correction below the surface code threshold. Nature, 638(8052), 920-926.

R&R: Caune, L., et al (2024). Demonstrating real-time and low-latency quantum error correction with superconducting qubits. arXiv preprint arXiv:2410.05202.

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Extrapolated Performance

  • Extrapolates with the performance of the Helios decoder and the measured communication latency

Introducing router layer

Expect sub-microsecond latency for 881 qubits

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Development Effort

Lines of HDL code: ~16000 lines in total

  • RISC-Q: ~ 13300 lines
  • QEC System: ~ 2500 lines on RISC-Q
    • Root Node: ~ 400 lines
    • Leaf Node: ~ 500 lines
    • Helios Decoder: ~ 1600 lines

​

~8 person-months for the QEC system implementation

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What does RISC-Q mean for everyone?

  • developers of SoCs: academic or industry, RISC-Q could be your design automation tool with improved productivity
  • experimental labs: RISC-Q could be more configurable than e.g., QubiC/QICK/ArtiQ to meet your customized needs
  • component contributors: RISC-Q provides a high-level language to implement components and a platform to share with others
  • system researchers: RISC-Q could provide a foundation, e.g., details of realistic quantum systems, for system research.

Hardware Integration Availability: incoming chassis w/ Xilinx RFSoC at roughly the 70% cost of QICK, 33% of Quantum Machines, …. but with full customization ability supported by RISC-Q.

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Ongoing RISC-Q related development

  • Support QICK and QubiC: integration of RISC-Q core to existing QICK and Qubic interfaces
  • Generator of BP-variant Hardware QEC Decoder :an automatic pipeline to fine-tune BP-variants for customized codes and errors and generate their hardware implementation.
  • On-chip intelligent calibration and control: a system-level acceleration for scalable real-time and perpetual quantum devices calibration and control
  • High-level programming/debugging/simulation tool for RISC-Q (@Purdue)

Are you interested in implementing anything with RISC-Q?

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Thank you !!

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Example -- SoC generated by RSIC-Q

  • Dataflow of superconducting qubit measurement for illustration

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Challenge in Latency

  • Total budget for the measurement process:
    • < 1 us
  • Latency of typical kernel services in existing Real-Time OS:
    • 100ns ~ 2us (suppose running at ~1GHz)
  • Can not rely on existing software
  • HW-SW co-design is required

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https://www.ul.com/sis/blog/measuring-real-time-operating-system-performance-part-ii-comparing-freertos-vs-zephyr

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Example -- SoC generated by RSIC-Q

  • Dataflow of superconducting qubit measurement for illustration

Hardware Implementation

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Example

  • C Program for Measurement – Memory-mapped I/O approach

Software

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HW-SW Integration

  • Through Memory-Map I/O

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Memory-Map I/O

  •  

 

Measurement result of the 2nd qubit is loaded to the variable m

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Memory-Map I/O

  • Hardware – QCSoC generated by RISC-Q
    • SpinalHDL: Describe which port is mapped to which address

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    • Generated Verilog:

​

TileLink Bus Logic

Address Mapping

…

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Challenge in Throughput

  • Duration of a quantum gate: 10~100ns
  • A cycle of FPGA: 2ns
  • To apply more gates before decoherence:
    • Minimize gaps between gates (through Hardware Design)
    • Setup each gate in less cycles (through HW-SW co-design)

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Minimizing Gaps

  • Pipelined Implementation of Signal Generation
    • No gaps between gates

Fully Pipelined

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Reducing Cycles - Custom Instruction

  • MMIO takes multiple instruction to setup a pulse
  • Throughput is limited by the IPC of the CPU
  • RISC-Q implement custom instruction extension of RISC-V

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  • HW: Implement modular custom instructions using SpinalHDL
  • SW: Modified compiler toolchain to support new instruction, e.g., LLVM for C/C++ for RISC-V.
  • Software Compatibility vs Throughput

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Instruction that sends a signal through the signal generator with specific id