Analog and digital electronics�18CS33�

Module 3

Combinational Circuit Design

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Referred Books/Sources

• Charles H Roth and Larry L Kinney, Analog and Digital Electronics, Cengage Learning,2019
• Charles H Roth and Larry L Kinney, Fundamental of Logic Design, Cengage Learning, 2017.
• Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 7^th Edition, Tata McGraw Hill, 2015

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9:45 AM

Module-3

Combinational circuit design and simulation using gates

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Multiplexers, Decoders and Programmable Logic Devices

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Objectives

1. Draw a timing diagram for a combinational circuit with gate delays.
2. Define static 0- and 1-hazards and dynamic hazards. Given a combinational circuit, find all of the static 0- and 1-hazards. For each hazard, specify the order in which the gate outputs must switch in order for the hazard to actually produce a false output.
3. Given a switching function, realize it using a two-level circuit which is free of static and dynamic hazards (for single input variable changes).
4. Design a multiple-output NAND or NOR circuit using gates with limited fan-in.
5. Explain the operation of a logic simulator that uses four-valued logic.
6. Test and debug a logic circuit design using a simulator.

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COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES

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Review of Combinational Circuit Design

• The first step in the design of a combinational switching circuit is usually to set up a truth table which specifies the output(s) as a function of the input variables.
• For n input variables this table will have 2n rows.
• Next step is to derive simplified algebraic expressions for the output functions using Karnaugh maps, the Quine-McCluskey method, or a similar procedure.
• The simplified algebraic expressions are then manipulated into the proper form, depending on the type of gates to be used in realizing the circuit.
• The number of levels in a gate circuit is equal to the maximum number of gates through which a signal must pass when going between the input and output terminals.

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Review of Combinational Circuit Design

• The minimum sum of products (or product of sums) leads directly to a minimum two-level gate circuit.
• However, in some applications it is desirable to increase the number of levels by factoring (or multiplying out) because this may lead to a reduction in the number of gates or gate inputs.
• When a circuit has two or more outputs, common terms in the output functions can often be used to reduce the total number of gates or gate inputs.
• If each function is minimized separately, this does not always lead to a minimum multiple-output circuit.
• For a two-level circuit, Karnaugh maps of the output functions can be used to find the common terms.
• All of the terms in the minimum multiple-output circuit will not necessarily be prime implicants of the individual functions.
• When designing circuits with three or more levels, looking for common terms on the Karnaugh maps may be of little value.
• In this case, the designer will often minimize the functions separately and, then, use ingenuity to factor the expressions in such a way to create common terms.

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Review of Combinational Circuit Design

• Minimum two-level AND-OR, NAND-NAND, OR-NAND, and NOR-OR circuits can be realized using the minimum sum of products as a starting point.
• Minimum two-level OR-AND, NOR-NOR, AND-NOR, and NAND-AND circuits can be realized using the minimum product of sums as a starting point.
• Design of multi-level multiple-output NAND-gate circuits is most easily accomplished by first designing a circuit of AND and OR gates.
• Usually, the best starting point is the minimum sum-of-products expressions for the output functions.
• These expressions are then factored in various ways until an economical circuit of the desired form can be found.
• If this circuit has an OR gate at each output and is arranged so that an AND-gate (or OR-gate) output is never connected to the same type of gate, a direct conversion to a NAND-gate circuit is possible.
• Conversion is accomplished by replacing all of the AND and OR gates with NAND gates and then inverting any literals which appear as inputs to the first, third, fifth, . . . levels (output gates are the first level).

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Review of Combinational Circuit Design

• Similarly, design of multi-level, multiple-output NOR-gate circuits is most easily accomplished by first designing a circuit of AND and OR gates.
• In this case the best starting point is usually the minimum sum-of-products expressions for the complements of the output functions.
• After factoring these expressions to the desired form, they are then complemented to get expressions for the output functions, and the corresponding circuit of AND and OR gates is drawn.

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Design of Circuits with Limited Gate Fan-In

• In practical logic design problems, the maximum number of inputs on each gate (or the fan-in) is limited.
• Depending on the type of gates used, this limit may be two, three, four, eight, or some other number.
• If a two-level realization of a circuit requires more gate inputs than allowed, factoring the logic expression to obtain a multi-level realization is necessary.

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Design of Circuits with Limited Gate Fan-In

• Example:
• Realize f(a, b, c, d) = Σm(0, 3, 4, 5, 8, 9, 10, 14, 15) using three-input NOR gates

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• f′ = a′b′c′d + ab′cd + abc′ + a′bc + a′cd′

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Design of Circuits with Limited Gate Fan-In

f′ = a′b′c′d + ab′cd + abc′ + a′bc + a′cd′

• A two-level realization requires two four-input gates and one five-input gate. The expression for f ′ is factored to reduce the maximum number of gate inputs to three and, then, it is complemented:

f ′ = b′d(a′c′ + ac) + a′c(b + d′) + abc′

f = [b + d′ + (a + c)(a′ + c′)][a + c′ + b′d][a′ + b′ + c]

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Design of Circuits with Limited Gate Fan-In

• The techniques for designing two-level, multiple-output circuits are not very effective for designing multiple-output circuits with more than two levels.
• Even if the two-level expressions had common terms, most of these common terms would be lost when the expressions were factored.
• Therefore, when designing multiple-output circuits with more than two levels, it is usually best to minimize each function separately.
• The resulting two-level expressions must then be factored to increase the number of levels.
• This factoring should be done in such a way as to introduce common terms wherever possible.

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Design of Circuits with Limited Gate Fan-In

• Example
• Realize the functions given below, using only two-input NAND gates and inverters. If we minimize each function separately, the result is

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Design of Circuits with Limited Gate Fan-In

f1 = b′c′ + ab′ + a′b

f2 = b′c′ + bc + a′b

f3 = a′b′c + ab + bc′

• Each function requires a three-input OR gate, so we will factor to reduce the number of gate inputs:

f1 = b′(a + c′) + a′b

f2 = b(a′ + c) + b′c′ or f2 = (b′ + c)(b + c′) + a′b

f3 = a′b′c + b(a + c′)

• The second expression for f2 has a term common to f1, so we will choose the second expression.
• We can eliminate the remaining three-input gate from f3 by noting that

a′b′c = a′(b′c) = a′(b + c′)′

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Design of Circuits with Limited Gate Fan-In

• Figure (a) shows the resulting circuit, using common terms a′b and a + c′.
• Because each output gate is an OR, the conversion to NAND gates, as shown in Figure (b).

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Gate Delays and Timing Diagrams

• When the input to a logic gate is changed, the output will not change instantaneously.
• The transistors or other switching elements within the gate take a finite time to react to a change in input, so that the change in the gate output is delayed with respect to the input change, this delay is called propagation delay.

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Gate Delays and Timing Diagrams

• Figure shows possible input and output waveforms for an inverter.
• If the change in output is delayed by time, ε , with respect to the input, we say that this gate has a propagation delay of ε.
• In practice, the propagation delay for a 0 to 1 output change may be different than the delay for a 1 to 0 change.
• Propagation delays for integrated circuit gates may be as short as a few nanoseconds (Negligible).

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Gate Delays and Timing Diagrams

• Timing diagrams are frequently used in the analysis of sequential circuits with respect to time (like memory circuits E.g. Flip-Flop, RAM).
• These diagrams show various signals in the circuit as a function of time.
• Several variables are usually plotted with the same time scale so that the times at which these variables change with respect to each other can easily be observed.

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Gate Delays and Timing Diagrams

• Figure shows the timing diagram for a circuit with two gates.
• Each gate has a propagation delay of 20 ns (nanoseconds).
• This timing diagram indicates what happens when gate inputs B and C are held at constant values 1 and 0, respectively, and input A is changed to 1 at t = 40 ns and then changed back to 0 at t = 100 ns.
• The output of gate G1 changes 20 ns after A changes, and the output of gate G2 changes 20 ns after G1 changes.

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Gate Delays and Timing Diagrams

• Figure shows a timing diagram for a circuit with an added delay element.
• The input X consists of two pulses, the first of which is 2 microseconds (2 × 10⁻⁶ second) wide and the second is 3 microseconds wide.
• The delay element has an output Y which is the same as the input except that it is delayed by 1 microsecond.

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Gate Delays and Timing Diagrams

• That is, Y changes to a 1 value 1 microsecond after the rising edge of the X pulse and returns to 0 1 microsecond after the falling edge of the X pulse.
• The output (Z) of the AND gate should be 1 during the time interval in which both X and Y are 1.
• If we assume a small propagation delay in the AND gate (ε), then Z will be as shown in Figure

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Hazards in Combinational Logic

• When the input to a combinational circuit changes, unwanted switching transients may appear in the output.
• These transients occur when different paths from input to output have different propagation delays.

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Hazards in Combinational Logic

• If, in response to any single input change and for some combination of propagation delays, a circuit output may momentarily go to 0 when it should remain a constant 1, we say that the circuit has a static 1-hazard.
• Similarly, if the output may momentarily go to 1 when it should remain a 0, we say that the circuit has a static 0-hazard.
• If, when the output is supposed to change from 0 to 1 (or 1 to 0), the output may change three or more times, we say that the circuit has a dynamic hazard.

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Hazards in Combinational Logic Static 1-hazard

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• If A = C = 1, then F = B + B′ = 1, so the F output should remain a constant 1 when B changes from 1 to 0.
• If each gate has a propagation delay of 10 ns

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Hazards in Combinational Logic Static 1-hazard

• Static 1-hazard

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Hazards in Combinational Logic Static 1-hazard

• E will go to 0 before D goes to 1, resulting in a momentary 0 (a glitch caused by the 1-hazard) appearing at the output F.
• Note that right after B changes to 0, both the inverter input (B) and output (B′) are 0 until the propagation delay has elapsed.
• During this period, both terms in the equation for F are 0, so F momentarily goes to 0.

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Hazards in Combinational Logic Static 1-hazard

• Note that hazards are properties of the circuit and are independent of the delays existing in the circuit.
• If the circuit is free of hazards, then for any combination of delays that might exist in the circuit and for any single input change, the output will not contain a transient.
• If a circuit contains a hazard, then there is some combination of delays and some input change for which the circuit output contains a transient.

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Hazards in Combinational Logic Static 1-hazard

• How to remove Hazard
• Assume the inverter has a delay of 2 ns rather than 10 ns.
• Then the D and E changes reaching the output OR gate are 2 ns apart, in which case the OR gate may not generate the 0 glitch.
• Hazards can be detected using a Karnaugh map

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Hazards in Combinational Logic Static 1-hazard

• As seen on the map, no loop covers both minterms ABC and AB′C.
• So if A = C = 1 and B changes, both terms can momentarily go to 0, resulting in a glitch in F.

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Hazards in Combinational Logic Static 1-hazard

• Detect hazards in a two-level AND-OR circuit, using the following procedure:
• Write down the sum-of-products expression for the circuit.
• Plot each term on the map and loop it.
• If any two adjacent 1’s are not covered by the same loop, a 1-hazard exists for the transition between the two 1’s. For an n-variable map, this transition occurs when one variable changes and the other n − 1 variables are held constant.

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Hazards in Combinational Logic Static 1-hazard

• If we add a loop to the redundant map and, then, add the corresponding gate to the circuit, this eliminates the hazard.
• The term AC remains 1 while B is changing, so no glitch can appear in the output.
• Note that F is no longer a minimum sum of products.

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Hazards in Combinational Logic Static 0-hazard

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• F = (A + C)(A′ + D′)(B′ + C′ + D)

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Hazards in Combinational Logic Static 0-hazard

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Hazards in Combinational Logic Static 0-hazard

• We can eliminate the 0-hazards by looping additional prime implicants that cover the adjacent 0’s that are not already covered by a common loop.
• This requires three additional loops as shown in Figure.
• The resulting equation is

F = (A + C)(A′ + D′)(B′ + C′ + D)(C + D′)(A + B′ + D)(A′ + B′ + C′)

• and the resulting circuit requires seven gates in addition to the inverters.

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Hazards in Combinational Logic Dynamic hazard

• Hazards in circuits with more than two levels can be determined by deriving either a SOP or POS expression for the circuit that represents a two-level circuit containing the same hazards as the original circuit.
• The SOP or POS expression is derived in the normal manner except that the complementation laws are not used, i.e., xx′ = 0 and x + x′ = 1 are not used.

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Hazards in Combinational Logic Dynamic hazard

• So, the resulting SOP (POS) expression may contain products (sums) of the form xx′α (x + x′ + β).
• Where α is a product of literals or it may be null; β is a sum of literals or it may be empty.
• The complementation laws are not used because we are analyzing the circuit behavior resulting from an input change.
• As that input change propagates through the circuit, at a given point in time a line tending toward the value x may not have the value that is the complement of a line tending toward the value x′.
• In the SOP expression, a product of the form xx′α represents a pseudo gate that may temporarily have the output value 1 as x changes and if α = 1.

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Hazards in Combinational Logic Dynamic hazard

• Given the SOP expression, with a two-level AND-OR circuit, for that:
• A static 1-hazard exists if the products are mapped on a Karnaugh map and if two 1’s are adjacent on the map and not included in one of the products.
• A static 0-hazard exists if there are two adjacent 0’s on the Karnaugh map for which α = 1 and the two input combinations differ just in the value of x.
• The circuit can have a static 0-hazard or a dynamic hazard only if the SOP expression contains a term of the form xx′α.

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Hazards in Combinational Logic Dynamic hazard

• A dynamic hazard exists if there is a term of the form xx′α and two conditions are satisfied:
• (1) There are adjacent input combinations on the Karnaugh map differing in the value of x, with α = 1 and with opposite function values.
• (2) for these input combinations the change in x propagates over at least three paths through the circuit.

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Hazards in Combinational Logic Dynamic hazard

• Example:

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POS Expression

f= (c′ + ad′ + bd′)(c + a′d + bd)

= cc′ + acd′ + bcd′ + a′c′d + aa′dd′ + a′bdd′ + bc′d + abdd′ + bdd′ = cc′ + acd′ + bcd′ + a′c′d + aa′dd′ + bc′d + bdd′

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Hazards in Combinational Logic Dynamic hazard

• The Karnaugh map for previous slide example is shown as the circled 1’s .
• The circuit does not contain any static 1-hazards because each pair of adjacent 1’s are covered by one of the product terms.

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Hazards in Combinational Logic Dynamic hazard

• Will check The terms cc′ and bdd′ may cause either static 0- or dynamic hazards or both.
• First for c changing and the second for d changing.
• The term aa′dd′ cannot cause either hazard because, for example, if a changes the dd′ part of the product forces it to 0.
• With a = 0, b = 0, and d = 0 and c changing, the circuit output is 0 before and after the change, and because the cc′ term can cause the output to temporarily become 1, this transition is a static 0-hazard.
• Similarly, a change in c, with a = 1, b = 0, and d = 1, is a static 0-hazard.
• The cc′ term cannot cause a dynamic hazard because there are only two physical paths from input c to the circuit output.

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Hazards in Combinational Logic Dynamic hazard

• Lets check the term bdd′ can cause a static 0- or dynamic hazard only if b = 1.
• From the Karnaugh map, it is seen that, with b = 1 and d changing, the circuit output changes for any combination of a and c, so the only possibility is that of a dynamic hazard.
• There are four physical paths from d to the circuit output, so a dynamic hazard exists if a d change can propagate over at least three of those paths.

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Hazards in Combinational Logic Dynamic hazard

• However, this cannot happen because, with c = 0, propagation over the upper two paths is blocked at the upper OR gate because c′ = 1 forces the OR gate output to be 1,
• With c = 1 propagation over the lower two paths is blocked at the lower OR gate.
• The circuit does not contain a dynamic hazard.

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Hazards in Combinational Logic Dynamic hazard

• Another approach to finding the hazards is as follows:

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• POS expression of K-Map is
• f = (c′ + a + b)(c′ + d′)(c + a′ + b)(c + d)
• Plotting the 0’s of f from this expression on a Karnaugh map reveals that there are 0-hazards when a = b = d = 0 and c changes, and also when b = 0, a = d = 1, and c changes.
• An expression of the form x + x′ does not appear in any sum term of f, and this indicates that there are no 1-hazards or dynamic hazards.

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Hazards in Combinational Logic Dynamic hazard

• Consider the example to find static and dynamic hazards
• f = (A′C′ + B′C) (C + D) = A′CC′ + A′C′D + B′C

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Hazards in Combinational Logic Dynamic hazard

• The Karnaugh map for f in Figure (b) shows that f = 1 for the input combinations (A, B, C, D) = (0, 0, 0, 1) and (0, 0, 1, 1) and neither product of f covers these two minterms; hence, these two input combinations imply a static 1-hazard for C changing.
• The product A′CC′ in f indicates the possibility of a static 0-hazard and a dynamic hazard for A = 0 and C changing.

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Hazards in Combinational Logic Dynamic hazard

• The Karnaugh map shows that when f = 0, the two input combinations (0, 1, 0, 0) and (0, 1, 1, 0) meet these conditions and, hence, they imply a static 0-hazard.

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Hazards in Combinational Logic Dynamic hazard

• The Karnaugh map shows two pairs of input combinations with f changing for A = 0 and C changing namely, (0, 0, 0, 0), (0, 0, 1, 0), and (0, 1, 0, 1), (0, 1, 1, 1).
• In order for these to be dynamic hazards, the C change must propagate over three or more paths to the output.
• The circuit shows that propagation over the three paths requires B = 0 and D = 0 as well as A = 0; thus, a dynamic hazard only occurs for (0, 0, 0, 0) and (0, 0, 1, 0).
• For (0, 1, 0, 1) and (0, 1, 1, 1), the C change only propagates over one path, and f can only change once.

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Hazards in Combinational Logic Dynamic hazard

• To design a circuit which is free of static and dynamic hazards, the following procedure may be used:
• Find a sum-of-products expression (F^t) for the output in which every pair of adjacent 1’s is covered by a 1-term. (The sum of all prime implicants will always satisfy this condition.) A two-level AND-OR circuit based on this F^t will be free of 1-, 0-, and dynamic hazards.
• If a different form of the circuit is desired, manipulate F^t to the desired form by simple factoring, DeMorgan’s laws, etc. Treat each x_i and x′_i as independent variables to prevent introduction of hazards.

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Hazards in Combinational Logic Dynamic hazard

• The hazards and the possibility of resulting glitches in this section has assumed that only a single input can change at a time and that no other input will change until the circuit has stabilized.
• If more than one input can change at one time, then nearly all circuits will contain hazards, and they cannot be eliminated by modifying the circuit implementation.

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Simulation and Testing of Logic Circuits

• Verifying the logic design to correct and debugging the design if necessary.
• Logic circuits may be tested either by actually building them or by simulating them on a computer.
• Simulation is generally easier, faster, and more economical.
• As logic circuits become more and more complex, it is very important to simulate a design before actually building it
• E.g IC or Chip Design
• Simulation is done for several reasons,
1. verification that the design is logically correct
2. verification that the timing of the logic signals is correct
3. simulation of faulty components in the circuit as an aid to finding tests for the circuit.

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Simulation and Testing of Logic Circuits

• To use a computer program for simulating logic circuits,
• you must first specify the circuit components and connections; then, specify the circuit inputs; and, finally, observe the circuit outputs.
• The circuit description may be input into a simulator in the form of a list of connections between the gates and other logic elements in the circuit, or the description may be in the form of a logic diagram drawn on a computer screen.

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Simulation and Testing of Logic Circuits

• A simple simulator for combinational logic works as follows:
• The circuit inputs are applied to the first set of gates in the circuit, and the outputs of those gates are calculated.
• The outputs of the gates which changed in the previous step are fed into the next level of gate inputs. If the input to any gate has changed, then the output of that gate is calculated.
• Step 2 is repeated until no more changes in gate inputs occur. The circuit is then in a steady-state condition, and the outputs may be read.
• Steps 1 through 3 are repeated every time a circuit input changes.

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Simulation and Testing of Logic Circuits

• The two logic values, 0 and 1, are not sufficient for simulating logic circuits.
• At times, the value of a gate input or output may be unknown, and we will represent this unknown value by X.
• At other times we may have no logic signal at an input, as in the case of an open circuit when an input is not connected to any output. We use the logic value Z to represent an open circuit, or high impedance (hi-Z) connection.
• The discussion that follows assumes we are using a four-valued logic simulator with logic values 0, 1, X (unknown), and Z (hi-Z).

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Simulation and Testing of Logic Circuits

• Example

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Simulation and Testing of Logic Circuits

• In Figure (b), one gate has no connection to one of its inputs.
• Because that gate has a 1 input and a hi-Z input, we do not know what the hardware will do, and the gate output is unknown.
• This is indicated by an X in the probe

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Simulation and Testing of Logic Circuits

• AND and OR Functions for Four-Valued Simulation
• For an AND gate,
• if one of the inputs is 0, the output is always 0 regardless of the other input.
• If one input is 1 and the other input is X (we do not know what the other input is), then the output is X (we do not know what the output is).
• If one input is 1 and the other input is Z (it has no logic signal), then the output is X (we do not know what the hardware will do).
• For an OR gate,
• if one of the inputs is 1, the output is 1 regardless of the other input.
• If one input is 0 and the other input is X or Z, the output is unknown.

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Simulation and Testing of Logic Circuits

• If a circuit output is wrong for some set of input values, this may be due to several possible causes:
• Incorrect design
• Gates connected wrong
• Wrong input signals to the circuit If the circuit is built in lab, other possible causes include
• Defective gates
• Defective connecting wires

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Simulation and Testing of Logic Circuits

• Logic Circuit with Incorrect Output then how to troubleshoot
• If the output gate has the wrong output and its inputs are correct, this indicates that the gate is defective.
• If one of the inputs is wrong, then either the gate is connected wrong, the gate driving this input has the wrong output, or the input connection is defective.

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Simulation and Testing of Logic Circuits

• The function F = AB(C′D + CD′) + A′B′(C + D) is realized by the circuit of

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Simulation and Testing of Logic Circuits

• For A = B = C = D = 1, the output F = 1 has the wrong value.
• The reason for the incorrect value of F can be determined as follows:
• The output of gate 7 (F ) is wrong, but this wrong output is consistent with the inputs to gate 7, that is, 1 + 0 = 1. Therefore, one of the inputs to gate 7 must be wrong.
• In order for gate 7 to have the correct output (F = 0), both inputs must be 0. Therefore, the output of gate 5 is wrong. However, the output of gate 5 is consistent with its inputs because 1 · 1 · 1 = 1. Therefore, one of the inputs to gate 5 must be wrong.
• Either the output of gate 3 is wrong, or the A or B input to gate 5 is wrong. Because C′D + CD′ = 0, the output of gate 3 is wrong.
• The output of gate 3 is not consistent with the outputs of gates 1 and 2 because 0 + 0 ≠ 1. Therefore, either one of the inputs to gate 3 is connected wrong, gate 3 is defective, or one of the input connections to gate 3 is defective.

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MULTIPLEXERS, DECODERS AND PROGRAMMABLE LOGIC DEVICES

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Objective

1. Explain the function of a multiplexer. Implement a multiplexer using gates.
2. Explain the operation of three-state buffers. Determine the resulting output when three-state buffer outputs are connected together. Use three-state buffers to multiplex signals onto a bus.
3. Explain the operation of a decoder and encoder. Use a decoder with added gates to implement a set of logic functions. Implement a decoder or priority encoder using gates.
4. Explain the operation of a read-only memory (ROM). Use a ROM to implement a set of logic functions.
5. Explain the operation of a programmable logic array (PLA). Use a PLA to implement a set of logic functions. Given a PLA table or an internal connection diagram for a PLA, determine the logic functions realized.
6. Explain the operation of a programmable array logic device (PAL). Determine the programming pattern required to realize a set of logic functions with a PAL.

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Inroduction

• Use of more complex integrated circuits (ICs) in logic design
• Integrated circuits may be classified
• Small-scale integration (SSI), Medium-scale integration (MSI), Large-scale integration (LSI), or Very-large-scale integration (VLSI), depending on the number of gates in each integrated circuit package and the type of function performed.
• SSI functions include NAND, NOR, AND, and OR gates, inverters, and flip-flops. SSI integrated circuit packages typically contain one to four gates, six inverters, or one or two flip-flops.
• MSI integrated circuits, such as adders, multiplexers, decoders, registers, and counters, perform more complex functions. Such integrated circuits typically contain the equivalent of 12 to 100 gates in one package.
• More complex functions such as memories and microprocessors are classified as LSI or VLSI integrated circuits.
• LSI integrated circuit generally contains 100 to a few thousand gates in a single package, and a
• VLSI integrated circuit contains several thousand gates or more.

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MULTIPLEXERS-1

• Multiplex means many into one.
• A multiplexer (also called data selector) is a circuit with many inputs but only one output. By applying control signals (Select Input), can steer any input to the output.
• Below shows the block diagram of MUX. The circuit has n input signals, m control signals and 1 output signal. Note that, m control signals can select at the most 2^m input signals thus n ≤ 2^m .

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MULTIPLEXERS-2

• The block diagram of a 4-to-1 multiplexer is shown below and its truth table.
• Depending on control inputs A, B one of the four inputs Do to D3 is steered to output Y.

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MULTIPLEXERS-2

• 2-to-1 Multiplexer and Switch Analog
• When the control input A is 0, the switch is in the upper position and the MUX output is Z = I₀;
• When A is 1, the switch is in the lower position and the MUX output is Z = I₁.
• In other words, a MUX acts like a switch that selects one of the data inputs (I₀ or I₁) and transmits it to the output.

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• Z = A′I₀ + AI₁

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MULTIPLEXERS-3

• 4-to-1 MUX logic circuit
• Logic equation of this circuit is a SOP representation.

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• Z = A′B′I₀ + A′BI₁ + AB′I₂ + ABI₃

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MULTIPLEXERS-3

• 4-to-1 MUX logic circuit
• Logic equation of this circuit is a SOP representation.

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MULTIPLEXERS-4

• In other words, for AB = 00, the first AND gate to which D0 is connected remains active and equal to Do and all other AND gate are inactive with output held at logic 0.
• Thus, multiplexer output Y is same as D0. If D0 =0, Y=0 and if D0 = 1, Y= 1.
• Commercial multiplexers ICs come in integer power of 2, e.g. 2-to-1, 4-to-1, 8-to- 1, 16-to-1 multiplexers.
• Write the 2 to 1 MUX block diagram, equation and it truth table.

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MULTIPLEXERS-4

• In general, a multiplexer with n control inputs can be used to select any one of 2ⁿ data inputs.
• The general equation for the output of a MUX with n control inputs and 2ⁿ data inputs is

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• where m_k is a minterm of the n control variables and I_k is the corresponding data input.

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MULTIPLEXERS-4

• 8-to-1 multiplexer

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• Z = A′B′C′I₀ + A′B′CI₁ + A′BC′I₂ + A′BCI₃ + AB′C′I₄ + AB′CI₅ + ABC′I₆ + ABCI₇

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MULTIPLEXERS-4

• Logic Diagram for 8-to-1 MUX

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MULTIPLEXERS-4

• Invert the data inputs
• If the OR gate in Figure is replaced by a NOR gate, then the 8-to-1 MUX inverts the selected input.
• Another type of multiplexer has an additional input called an enable.
• The 8-to-1 MUX in Figure can be modified to include an enable by changing the AND gates to five-input gates.
• The enable signal E is connected to the fifth input of each of the AND gates. Then, if E = 0, Z = 0 independent of the gate inputs I_i and the select inputs a, b, and c.
• However, if E = 1, then the MUX functions as an ordinary 8-to-1 multiplexer.
• The terminology used for the MUX output, i.e., active high and active low, can be used for the enable as well.

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MULTIPLEXERS-4

• Active-High, Active-Low Enable and Output Combinations

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MULTIPLEXERS-4

• Quad Multiplexer Used to Select Data
• A quadruple 2-to-1 MUX is used to select one of two 4-bit data words.
• If the control is A = 0, the values of x0, x1, x2, and x3 will appear at the z0, z1, z2, and z3 outputs
• If A = 1, the values of y0, y1, y2, and y3 will appear at the outputs.

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MULTIPLEXERS-4

• Implement using NAND gate

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• Z = A′B′C′I0 + A′B′CI1 + A′BC′I2 + A′BCI3 + AB′C′I4 + AB′CI5 + ABC′I6 + ABCI7
• Implement using NAND gate
• Z = A′B′(C′I0 + CI1) + A′B(C′I2 + CI3) + AB′(C′I4 + CI5) + AB(C′I6+CI7)

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MULTIPLEXERS-4

• Note that the data inputs are connected to four 2-to-1 MUXs with C as the select line, and the outputs of these 2-to-1 MUXs are connected to a 4-to-1 MUX with A and B as the select lines. Figure shows this in block diagram form.

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MULTIPLEXERS-6

• IC 74151

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MULTIPLEXERS-7

• Lab Experiment
• Given Logic expression is f(a,b,c,d)=Σm(2,3,4,5,13,15)+d(8,9,10,11) Use the Entered Variable Map (EVM) technique.

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MULTIPLEXERS-8

• Final Circuit diagram

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MULTIPLEXERS-9

• Show how 4-to-1 multiplexer can be obtained using only 2-to-1 multiplexer.
• Logic equation for 2-to-1Multiplexer: Y= A’D0 + AD1
• Logic equation for 4-to-1 Multiplexer: Y = A'B' D0+ A'BD1 + AB' D2 + ABD3
• This can be rewritten as, Y= A'(B'D0 + BD1) +A (B'D2 + BD3)

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MULTIPLEXERS-10

• Realize Y=A'B + B'C' + ABC using an 8-to-1 multiplexer.
• First we express Y as a function of minterms of three variables. Thus
• Y = A'B + B'C' + ABC
• Y =A'B(C' + C)+B'C'(A' + A)+ ABC [As,X+X'= I]
• Y = A'B'C' + A'BC' + A'BC + AB'C' + ABC
• Comparing this with equation of 8 to 1 multiplexer, we find by substituting D0 = D2 = D3 =D4 = D7 = 1 and D1 = D5 = D6 = 0.

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MULTIPLEXERS-11

• Can it be realized Y =A'B + B'C‘ + ABC equation with a 4-to-1 multiplexer?
• The 4-to-1 multiplexer generates 4 minterms for different combinations of AB. We rewrite given logic equation in such a way that all these terms are present in the equation.
• Y =A'B+B'C' +ABC
• Y =A'B+ B'C'(A' +A)+ ABC [As,X +X' = I]
• Y =A'B'.C' + A'B.1 +AB'.C' + AB.C
• Compare above with equation of a 4-to-1 multiplexer. We see D0= C', D1 = 1, D2 = C' and D3 = C generate the given logic function.

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MULTIPLEXERS-12

• Design a 32-to-1 multiplexer using two 16-to-1 multiplexers and one 2-to-1 multiplexer.
• A 32-to-1 multiplexer requires log2³² =5 select lines say, ABCDE. The Iower 4 select lines BCDE choose 16-to-1 multiplexer outputs. The 2-to-1 multiplexer chooses one of the output of two 16-to-1 multiplexers depending on what appears in the 5th select line, A.

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Three-State Buffers

• A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system.
• A simple buffer may be used to increase the driving capability of a gate output.

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Three-State Buffers

• A buffer connected between a gate output and several gate inputs.
• Because no bubble is present at the buffer output, this is a noninverting buffer, and the logic values of the buffer input and output are the same, that is, F = C.

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Three-State Buffers

• Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other.
• For example, if one gate has a 0 output (a low voltage) and another has a 1 output (a high voltage), when the Gate outputs are connected together the resulting output voltage may be some intermediate value that does not clearly represent either a 0 or a 1.
• In some cases, damage to the gates
• Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together.

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Three-State Buffers

• Three-state buffers are also called tri-state buffers.

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• When B= 1 then C = A
• When B= 0 then C = Z (Hi-Z high-impedance)

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Three-State Buffers

• Four Kinds of Three-State Buffers

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Three-State Buffers

• Data Selection Using Three-State Buffers

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• D = B′A + BC

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Three-State Buffers

• Circuit with Two Three-State Buffers
• When we connect two three-state buffer outputs together, as shown in Figure, if one of the buffers is disabled (output = Z), the combined output F is the same as the other buffer output.
• If both buffers are disabled, the output is Z. If both buffers are enabled, a conflict can occur.

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Three-State Buffers

• A multiplexer may be used to select one of several sources to drive a device input.
• For example, if an adder input must come from four different sources, a 4-to-1 MUX may be used to select one of the four sources.
• An alternative is to set up a three-state bus, using three-state buffers to select one of the sources.

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Three-State Buffers

• Integrated Circuit with Bi-Directional Input-Output Pin
• Bi-directional means that the same pin can be used as an input pin and as an output pin, but not both at the same time.
• To accomplish this, the circuit output is connected to the pin through a three-state buffer, as shown in Figure.

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• When the buffer is enabled, the pin is driven with the output signal. When the buffer is disabled, an external source can drive the input pin.

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DECODER-1

• A decoder is similar to a demultiplexer, with one exception-there is no data input.
• Also called binary-to-decimal decoder.
• The name decoder means translating of coded information from one format into another.
• A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2ⁿ output code. 
• Depending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-bit codes. Upon the availability of 2ⁿ lines, it activates the one of its output by deactivating (making logic 0) all other input whenever it receives n inputs.

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DECODER-2

• The most commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to-16 line binary decoder.
• 2-to-4 decoder also called 1 of 4
• 3-to-8 decoder also called 1 of 8
• 4-to-16 line binary decoder also called 1 of 16

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DECODER-3

• 2-to-4 Binary Decoder (1 of 4 Decoder)

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DECODER-4

• 3-to-8 Binary Decoder (1 of 8 Decoder)

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DECODER-5

• This decoder generates all of the minterms of the three input variables. Exactly one of the output lines will be 1 for each combination of the values of the input variables.

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DECODER-5

• A 4-to-10 Line Decoder

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DECODER-5

• A 4-to-10 Line Decoder

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DECODER-5

• A 4-to-10 Line Decoder
• This decoder has inverted outputs (indicated by the small circles).
• For each combination of the values of the inputs, exactly one of the output lines will be 0.
• When a binary-coded-decimal (BCD) digit is used as an input to this decoder, one of the output lines will go low to indicate which of the 10 decimal digits is present.

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DECODER-6

• In general, an n-to-2ⁿ line decoder generates all 2ⁿ minterms (or maxterms) of the n input variables. The outputs are defined by the equations

yi = mi = Mi ′, i = 0 to 2n − 1 (noninverted outputs)

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yi = mi ′ = Mi, i = 0 to 2n − 1 (inverted outputs)

• where mi is a minterm of the n input variables and Mi is a maxterm.

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DECODER-6

• Applications of Decoders
• Decoders are greatly used in applications where the particular output or group of outputs to be activated only on the occurrence of a specific combination of input levels.
• Binary to Decimal Decoder
• Decoders are used to get the decimal digit corresponding to a specific input combination. A BCD number needs 4 binary digits to represent the 0 to 9 decimal digits, thus it consists of 4 input lines. It consists of 10 output lines corresponding to 0 to 9 decimal digits. (1 of 10 line decoder)
• Address Decoders
• Amongst its many uses, a decoder is widely used to decode the particular memory location in the computer memory system. Decoders accept the address code generated by the CPU which is a combination of address bits for a specific location in the memory. In a memory system, there are several memory ICs are combined and each one has their unique address to distinguish from other memory locations. In such cases a decoder built in the memory ICs circuitry, is used to select a memory IC in response to a range of addresses by decoding the most significant bits of the systems address, thereby a particular memory location or IC is selected.
• Instruction Decoder
• Another application of the decoder can be found in the control unit of the central processing unit. This decoder is used to decode the program instructions in order to activate the specific control lines such that different operations in the ALU of the CPU are carried out.

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DECODER-6

• Because an n-input decoder generates all of the minterms of n variables, n- variable functions can be realized by ORing together selected minterm outputs from a decoder.
• If the decoder outputs are inverted, then NAND gates can be used to generate the functions.

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DECODER-6

• Realize f1(a, b, c, d) = m1 + m2 + m4 and
• f2(a, b, c, d) = m4 + m7 + m9 using the 4 to 10 line decoder.

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DECODER-7

• Show how using a 3-to-8 decoder and multi-input OR gates following Boolean expressions can be realized simultaneously.

F1 (A, B, C) = ∑m(0, 4, 6);

F2(A, B, C) = ∑m(0, 5);

F3(A, B, C) = ∑m(1, 2, 3, 7)

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DECODER-8

• Implement a full adder circuit using a 3-to-8 line decoder.
• Sum output S = ∑m(1 2 4 7)
• Carry output Co= ∑m(3 5 6 7)

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DECODER-9

• BCD-TO-DECIMAL DECODERS (IC 7445)

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DECODER-10

• Truth Table of 1 of 10 decoder

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ENCODERS-1

• An encoder converts an active input signal into a coded output signal.
• An encoder is a device which converts familiar numbers or characters or symbols into a coded format. It accepts the alphabetic characters and decimal numbers as inputs and produces the outputs as a coded representation of the inputs.
• It is a combinational circuit that performs the opposite function of a decoder.
• These are mainly used to reduce the number of bits needed to represent given information.

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ENCODERS-2

• Depending on the number of input lines, digital or binary encoders produce the output codes in the form of 2 or 3 or 4 bit codes.
• An encoder is a multiplexer without its single output line.
• It is a combinational logic function that has 2ⁿ (or fewer) input lines and n output lines, which correspond to n selection lines in a multiplexer.
• The n output lines generate the binary code for the possible 2ⁿ input lines.

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ENCODERS-3

• 4 – to – 2 Bit Binary Encoder

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ENCODERS-3

• An 8-to-3 Priority Encoder

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ENCODERS-3

• An 8-to-3 Priority Encoder
• 8-to-3 priority encoder with inputs y0 through y7.
• If input yi is 1 and the other inputs are 0, then the abc outputs represent a binary number equal to i.
• For example, if y3 = 1, then abc = 011.
• If more than one input can be 1 at the same time, the output can be defined using a priority scheme.
• The truth table uses the following scheme:
• If more than one input is 1, the highest numbered input determines the output.
• For example, if inputs y1, y4, and y5 are 1, the output is abc = 101.
• The X’s in the table are don’t-cares; for example, if y5 is 1, we do not care what inputs y0 through y4 are.
• Output d is 1 if any input is 1, otherwise, d is 0.
• This signal is needed to distinguish the case of all 0 inputs from the case where only y0 is 1.

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ENCODERS-4

• Decimal-to-BCD Encoder

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ENCODERS-4

• Decimal-to-BCD Encoder
• Y3 = D8 + D9
• Y2 = D4 + D5 + D6 + D7
• Y1 = D2 + D3 + D6 + D7
• Y0 = D1 + D3 + D5 + D7 + D9

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Read-Only Memories

• An 8-Word × 4-Bit ROM

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Read-Only Memories

• For each combination of input values on the three input lines, the corresponding pattern of 0’s and 1’s appears on the ROM output lines.
• For example, if the combination ABC = 010 is applied to the input lines, the pattern F₀F₁F₂F₃ = 0111 appears on the output lines.
• Each of the output patterns that is stored in the ROM is called a word.
• Because the ROM has three input lines, we have 2³ = eight different combinations of input values. Each input combination serves as an address which can select one of the eight words stored in the memory.
• Because there are four output lines, each word is four bits long, and the size of this ROM is 8 words × 4 bits.

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Read-Only Memories

• Read-Only Memory with n Inputs and m Outputs

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• A ROM which has n input lines and m output lines contains an array of 2ⁿ words, and each word is m bits long. The input lines serve as an address to select one of the 2ⁿ words.

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Read-Only Memories

• Basic ROM Structure

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• When a pattern of n 0’s and 1’s is applied to the decoder inputs, exactly one of the 2ⁿ decoder outputs is 1.
• This decoder output line selects one of the words in the memory array, and the bit pattern stored in this word is transferred to the memory output lines.

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Read-Only Memories

• An 8-Word × 4-Bit ROM

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Read-Only Memories

• An 8-Word × 4-Bit ROM
• The decoder generates the eight minterms of the three input variables.
• The memory array forms the four output functions by ORing together selected minterms.
• A switching element is placed at the intersection of a word line and an output line if the corresponding minterm is to be included in the output function; otherwise, the switching element is omitted (or not connected).
• If a switching element connects an output line to a word line which is 1, the output line will be 1.
• Otherwise, the pull-down resistors which cause the output line to be 0.

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Read-Only Memories

• An 8-Word × 4-Bit ROM
• So the switching elements which are connected in this way in the memory array effectively form an OR gate for each of the output functions.
• For example, m0, m1, m4, and m6 are ORed together to form F0. Figure shows the equivalent OR gate.

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Read-Only Memories

• An 8-Word × 4-Bit ROM
• In general, those minterms which are connected to output line F by switching elements are ORed together to form the output Fi.
• Thus, the ROM generates the following functions:
• F0 =Σ m(0, 1, 4, 6) = A′B′ + AC′
• F1 =Σ m(2, 3, 4, 6, 7) = B + AC′
• F2 =Σ m(0, 1, 2, 6) = A′B′ + BC′
• F3 =Σ m(2, 3, 5, 6, 7) = AC + B

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Read-Only Memories

• Multiple-output combinational circuits can easily be realized using ROMs.
• Example:
• Realize a code converter that converts a 4-bit binary number to a hexadecimal digit and outputs the 7-bit ASCII code.

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Read-Only Memories

• Truth table and logic circuit for the converter

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Read-Only Memories

• ROM Realization of Code Converter

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The switching elements at the intersections of the rows and columns of the memory array are indicated using X’s. An X indicates that the switching element is present and connected, and no X indicates that the corresponding element is absent or not connected.

Read-Only Memories

• The following diagram shows the pattern of 0’s and 1’s stored in a ROM with eight words and four bits per word. What will be the values of F1, F2, F3, and F4 if A = 0 and B = C = 1?

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• Give the minterm expansions for F1 and F2:
• F1=
• F2=

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Programmable Logic Devices (PLDs)

• ROMs
• Programmable Array Logic (PALs)
• Programmable logic arrays (PLAs)

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Programmable Array Logic (PAL)-1

• Programmable array logic (PAL) is a programmable array of logic gates on a single chip.
• PALs are another design solution, similar to a sum-of-products solution, product-of-sums solution, and multiplexer logic.
• A PAL has a programmable AND array and a fixed OR array.

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Programmable Array Logic (PAL)-1

• Figure represents a segment of an unprogrammed PAL

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• represents an input buffer which is logically equivalent to

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• When the PAL is programmed, some of the interconnection points are programmed to make the desired connections to the AND gate inputs. Connections to the AND gate inputs in a PAL are represented by X’s as shown:

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Programmable Array Logic (PAL)-1

• Realize the function
• I₁I₂′ + I₁′I₂
• The X’s in Figure indicate that I₁ and I₂′ lines are connected to the first AND gate, and the I₁′ and I₂ lines are connected to the other gate.

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Programmable Array Logic (PAL)-1

• Implementation of a Full Adder Using a PAL
• S_um =X′Y′C_in + X′YC′_in + XY′C′_in + XYC_in
• C_out = XC_in + YC_in + XY

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Programmable Array Logic (PAL)-2

• PAL with 4 inputs and 4 outputs
• In the x's on the input side are fusible links, while the solid black bullets on the output side are fixed connections.

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Programmable Array Logic (PAL)-3

• Example of how to program a PAL.

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• The first desired product is A’BC’D On the top input line in figure shown
• Remove the first x, the fourth x, the fifth x, and the eighth x.
• Then the top AND gate has an output of A’BC’D

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Programmable Logic Devices (PLDs)

• A programmable logic device (or PLD) is a general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions.
• PLDs are capable of realizing from 2 to 10 functions of 4 to 16 variables with a single integrated circuit.
• More complex PLDs may contain thousands of gates and flip-flops. Thus, a single PLD can replace a large number of integrated circuits, and this leads to lower cost designs.
• When a digital system is designed using a PLD, changes in the design can easily be made by changing the programming of the PLD without having to change the wiring in the system.

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Programmable Logic Arrays (PLAs)-1

• A PLA performs the same basic function as a ROM.
• A PLA with n inputs and m outputs can realize m functions of n variables.
• The internal organization of the PLA is the decoder is replaced with an AND array which realizes selected product terms of the input variables.
• The OR array ORs together the product terms needed to form the output functions, so a PLA implements a sum-of-products expression, while a ROM directly implements a truth table.

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Programmable Logic Arrays (PLAs)-1

• PLA with Three Inputs, Five Product Terms, and Four Outputs
• F0 =Σ m(0, 1, 4, 6) = A′B′ + AC′
• F1 =Σ m(2, 3, 4, 6, 7) = B + AC′
• F2 =Σ m(0, 1, 2, 6) = A′B′ + BC′
• F3 =Σ m(2, 3, 5, 6, 7) = AC + B

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Programmable Logic Arrays (PLAs)-1

• AND-OR Array Equivalent
• F0 =Σ m(0, 1, 4, 6) = A′B′ + AC′
• F1 =Σ m(2, 3, 4, 6, 7) = B + AC′
• F2 =Σ m(0, 1, 2, 6) = A′B′ + BC′
• F3 =Σ m(2, 3, 5, 6, 7) = AC + B

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Programmable Logic Arrays (PLAs)-1

• PLA table
• F0 =Σ m(0, 1, 4, 6) = A′B′ + AC′
• F1 =Σ m(2, 3, 4, 6, 7) = B + AC′
• F2 =Σ m(0, 1, 2, 6) = A′B′ + BC′
• F3 =Σ m(2, 3, 5, 6, 7) = AC + B
• The input side of the table specifies the product terms.
• The symbols 0, 1, and – indicate whether a variable is complemented, not complemented, or not present in the corresponding product term.
• The output side of the table specifies which product terms appear in each output function. A 1 or 0 indicates whether a given product term is present or not present in the corresponding output function.

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Programmable Logic Arrays (PLAs)-1

• Example PLA Realization of Equation
• f1 = a′bd + abd + ab′c′ + b′c
• f2 = c + a′bd
• f3 = bc + ab′c′ + abd

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A cross mark at the intersection of a word line and an input or output line indicates the presence of a switching element in the array.

Programmable Logic Arrays (PLAs)-1

• A PLA table is significantly different than a truth table for a ROM.
• In ROM truth table each row represents a minterm; therefore, exactly one row will be selected by each combination of input values.
• The 0’s and 1’s of the output portion of the selected row determine the corresponding output values.
• In a PLA table represents a general product term.
• Therefore, zero, one, or more rows may be selected by each combination of input values.
• To determine the value of fi for a given input combination, the values of fi in the selected rows of the PLA table must be ORed together.

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Programmable Logic Arrays (PLAs)-2

• An example, use a PLA to recognize each of the 10 decimal digits represented in binary form and to correctly drive a 7-segment display.
• Four bits (ABCD) are required to represent the 10 decimal numbers. There must be 7 outputs (abcdefg), 1 output to drive each of the 7 segments of the indicator.

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Programmable Logic Arrays (PLAs)-3

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Programmable Logic Arrays (PLAs)-4

• Implement the following Boolean function using suitable PLA f1= ∑(0,1,4,6), f2= ∑(2,3,4,6,7), f3= ∑(0,1,2,6), f4= ∑(2,3,5,6,7)
• Draw a PLA circuit simultaneously realize the Boolean function Y3=A’BC’; Y2=AC; Y1=AB’C+A’BC+ABC’; Y0=A’BC’+A’BC+A’B’C’+ABC.
• Draw a PLA circuit simultaneously realize the Boolean function X=A’B’C+AB’C’+B’C; Y=A’B’C+AB’C’; Z=B’C.
• Design 7-segment decoder using PLA.

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