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MAX 10 FPGAs

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Altera Continues Focus & Investment in Low End Families

2

Time

Cyclone IV

Future Product

FPGA/SoC

Cyclone V

FPGA /SoC

In Planning

MAX V

Non-Volatile Integration

Integration

Packaging

Performance, features & density

Bandwidth & SoC

MAX 10

Cyclone I0

More performance,

features, or density

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Traditional FPGA System Components

3

FPGA

Configuration

Images

ADC #1

ADC #2

32-bit�Processor

1.2 VDC�Power�Supply

2.5 VDC�Power�Supply

3.3 VDC�Power�Supply

Clock

Oscillator

Clock

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MAX 10 Simplifies Traditional FPGA Systems

4

FPGA

Configuration

Image

ADC #1

ADC #2

Program�Image Flash

32-bit�Processor

1.2 VDC�Power�Supply

2.5 VDC�Power�Supply

3.3 VDC�Power�Supply

Power�Regulator

Clock

Oscillator

Clock

Enpirion

Clock

50%

Board Area Reduction

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Lower BOM, Smaller PCB Area, Instant-on Configuration

5

Packages as

small as

3 x 3 mm

Up to 50K Logic Elements

RAM Blocks

12-bit SAR ADCs

8 I/O Banks

4 PLLs

User Flash

Configuration Flash 1

32-bit Processor

DSP Blocks

Power Regulator

Configuration Flash 2

Flash Memory (NOR)

On-chip Oscillator

DDR3 Controller

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MAX 10 FPGA Family

6

Device	LEs	Block Memory (Kbits)	18x18 Mults	PLLs	Internal Config.	User Flash ¹ (KBytes)	ADC, TSD	External RAM I/F
10M02	2,000	108	16	1, 2	Single	12	-	Yes ²
10M04	4,000	189	20	1, 2	Dual	16 – 156	1, 1	Yes ²
10M08	8,000	378	24	1, 2	Dual	32 – 172	1, 1	Yes ²
10M16	16,000	549	45	1, 4	Dual	32 – 296	1, 1	Yes ³
10M25	25,000	675	55	1, 4	Dual	32 – 400	2, 1	Yes ³
10M40	40,000	1,260	125	1, 4	Dual	64 – 736	2, 1	Yes ³
10M50	50,000	1,638	144	1, 4	Dual	64 – 736	2, 1	Yes ³

Preliminary and subject to change without notice.

Notes:

User Flash depends upon configuration option.
SRAM only.
SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2.
ADC blocks available on die but may not be available in low pin count packages.

Here is the family table showing the resources of the family…ranging from 2,000 user logic elements (LE’s)…an ample amount of logic resources for the majority of control plane, simple glue logic functions…all the way up to 50,000 LE’s.
There is an ample amount of on-chip RAM and FLASH memory…along with 18x18 multipliers that can be used for massively parallel DSP processing for things like filtering or image processing.
High performance, low-jitter PLLs and global clock networks provide lots of on-chip clocking resources.

The # of PLL’s available is dependent on the package option…lower pin-count packages only have 1 PLL, F256 or higher pin-count packages have the maximum number of PLLs available.
Not shown here but the # of global clocks available = 10 or 20 (10M02-08 has 10 clocks, 10M16-50 has 20 clocks).

All of the devices are self-configured and store the device configuration(s) within secure, integrated FLASH (this is NOT die stack…i.e. Xilinx Spartan-3AN).
Another 1^st for Altera…the inclusion of up to 2 on-chip analog blocks (ADC + temperature sensing diode).
For the larger densities devices, we’ve added some on-chip optimization to simplify creating I/O interfaces to external double data rate SDRAM memories.

Note 1 - Under certain conditions, additional on-chip FLASH memory will be available to the user…potentially another 500 Kbits up to 5 Mbits. This would be very useful for Nios CODE storage.

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MAX 10 FPGAs – Architectural Details

7

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Power supply variant differences

8

Feature	Single Supply Variant	Dual Supply Variant
Core Speed	Fmax = 100 MHz	Fmax = 150+ MHz
DSP	Up to 198 MHz	Up to 234 MHz
LVDS	200 – 400 Mbps	380 – 830 Mbps
EMIF	Not Supported	DDR2 / LPDDR2 @ 200 MHz DDR3 @ 300 MHz
RAM Blocks	Up to 232 MHz	Up to 330 MHz
DSP Blocks	Up to 198 MHz	Up to 310 MHz
PLLs	Single PLL support	Up to 4
Analog Block	SNR: 54 dB SINAD: 53 dB	SNR: 62 dB SINAD: 61.5 dB

Single supply devices optimized for Simplicity

Dual supply devices offer increased Performance

During the development of the MAX 10 chip, the power supply system of the chip was changed by reducing the required voltage levels for the operation of the chip. The MAX10 chip has two versions of the power supply system - with one power supply or with two.

In the first case, two separate power supplies are used, located on the board - 1.2 V and 2.5 V. In this case, we get a system that is a compromise between performance and energy consumption.

In the second case, we will use one external power supply, which has a range of output voltage from 3 V to 3.3 V. Inside the chip, this voltage is converted to the required 1.2 V. This solution reduces the number of external components on the board, and therefore, reduce its area and cost.

In the Single supply variant of MAX 10 FPGAs:

Performance is limited, both in the core and I/O

Analog features (such as PLL count and ADC ENOB) are also limited.

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Integrated Analog Blocks

In-chip system monitoring

Integrated ADCs
Reduce board space
Flexible sample sequencing
Lower latency

Measure environmental conditions

Integrated temperature sensor

9

Analog

Dedicated

Shared

Dedicated�Vref

Analog Inputs:

Analog Hard IP Block

In Max10, we have up to two SAR-architecture ADC’s. This architecture gives us good ratio of speed to power and is ideal for applications such as data acquisition and motor driving.

Integrating two Analog blocks in MAX 10 enable the device to perform in-chip system monitoring – such as sample sequencing, and measure environmental conditions – such as temperature control.

The analog blocks are both built into MAX 10, and supported within our Quartus II software. By using JTAG, customers can easily tap into the analog blocks within MAX 10 and easily debug the device. Our system Console feature in Quartus II guides the development of the analog blocks, while also providing a comprehensive debug tool kit. This all makes it very easy for customers to use the integrated analog in MAX 10.

The Analog blocks support two different functions, an Analog to Digital Converter (ADC) and a Temperature Sensing Diode (TSD). Each ADC supports 1 million samples per second and has up to 18 analog inputs:

16 channels (dual purpose pins, shared with GPIO)
1 dedicated channel per ADC
1 dedicated temp. sensing diode but for ADC1 only

Most of the Analog block’s inputs will use dual purpose I/O pins (and by dual purpose here, I mean either I/O for the FPGA or inputs for the analog block), but there will be two special, dedicated input pins to provide higher quality & precision. These two inputs will also come with analog pre-scalars, which allow measurement of analog signals greater than the normal input levels.

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Advantages of Hard IP Integration

The real world is analog

Integration of analog blocks allows direct mixed signal support
Reduce components count at front end

Benefits of Integration

Reduced device I/O count
GUI based configuration
Flexible sample sequence
Faster data output
Simultaneous Sampling

$$$ + space savings!

10

CPU1

Sensor CPU
low power
small form factor
Sensor Calibration
DSP Functions

Sensor

ADC

EEPROM

CPU1

Sensor CPU
low power
small form factor
Sensor Calibration
DSP Functions

Sensor

ADC

UFM

MAX10 FPGA

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An Overview of ADC Technologies

Three Main Types of ADC

Sigma Delta
Successive Approximation Register (SAR)
Pipeline

The selection of the right architecture is a very crucial decision
ADC’s are generally characterised in three ways

Bandwidth / Conversion Rate
Output Resolution
Input Voltage Range
Signal to Noise Ratio (SNR)

11

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Successive Approximation Register (SAR)

Advantages

Zero-cycle Latency
Low latency-time
High Accuracy
Low Power
Easy to use
Programmable alarm detection
System simulation support

ADC (SAR) Applications

Data Logging

Temperature sensors
Voltage sensors
Pressure sensors

Motor Control

Bridge Sensors

Displacement / Proximity measurement

12

The Real World is analog

The Successive Approximation (SAR) architecture, which is what has been selected for Max10, is very suitable applications such as data acquisition or Motor Control; they typically have resolutions ranging from 8bits to 18 bits and sampling rates ranging from 50 KHz to 5 MHz.
SAR Advantages:

Zero cycle latency Time

High Accuracy

Typically Low power

Easy to use

SAR Disadvantages

Max sample rates in the 2-5 MHz region typically

Lower SNR than Sigma Delta 96dB vs 64dB (SAR)

Sigma Delta converters are oversampling converters, performing well at an effective sampling frequency below 200KHz bandwidth often including on chip high filtering
Sigma Delta Advantages, higher SNR levels, much more complex filter functions readily achievable, used to perform additional DSP functions. Typical application for a Sigma Delta ADC would be wireless system IQ downlink where high SNR is required

Typical SAR Applications include

Motor Control

Battery Fuel Gauges

Power-Supply and System Monitoring

High speed sensors in Automotive Power Train and Safety applications

Rotational Sensors

Proximity Sensors

Accelerometers

Gyroscopes

Protective relays for power systems and power amplifier subsystems for communications

Even Building control systems

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Analog Hard IP Block

12-bit SAR ADC

Single or Dual mode operation

Supports simultaneous input sampling

18 Analog inputs

1 Dedicated analog I/O per ADC
16 Shared pads with GPIO

Includes pre-scaler channels

ADC Performance

SNR 62dB*
SINAD 61.5dB*
THD 70dB*

Variable sample rate

25Ksps to 1Msps (per ADC)

Temperature Sensing Diode

Operating Range -40°C to +125°C

* Note: with prescalar enabled is 6dB less

13

ADC measurement criteria definitions

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ADC Megawizard

Modular Design

ADC Block
Sequencer
Sample Store
Debug Port (Analog Toolkit)
Single or Dual ADC core

Input threshold detection

64 sample, fully programmable sequencer

Internal or external reference

14

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MAX 10 FPGA – Device Configuration

15

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Configuration Flash Memory (CFM)

Many Benefits to

Integrated Configuration Flash

Instant On Configuration
Single or Dual Configurations
Less Board Space
Smaller Bill of Materials

Reduces assembly costs
Simplified inventory management

Increased Security

No exposed external interface

16

MAX 10 FPGAs

FPGA Logic

Configuration

Flash Memory

User

Flash Memory

Figure Not to Scale

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MAX 10 Configuration �

17

CONFIG_SEL	Fallback	Description
On	On	Device will configure from CONFIG_SEL image (CFM0 or CFM1), if image fails to load, will configure from alternative image
On	Off	Device will configure from CONFIG_SEL image(CFM0 or CFM1), if images fails to load, device will stop and wait for reconfiguration
Off	On	Device will configure from CFM0, if configuration fails, will configure from CFM1
Off	Off	Device will configure from CFM0, if configuration fails, device will stop and wait for reconfiguration

cfm1

cfm0

Config Sel

Control Block

POR

nConfig

start

cfm0

2 Image System

cfm1

N

Y

Config_Sel

Enabled

N

Y

0

1

Config_Sel

status

CONFIG_SEL input pin selects one of two images from Configuration Flash Memory (CFM)

RU IP Block

Decrypt & Decompress Control

Fallback

Configuration start up flow

Configuration Data

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MAX 10 FPGA – User Flash Memory (UFM)

18

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UFM Block Overview

User Flash Memory Block

Up to 512 Kbits on largest device

Supports native 32-bit parallel interface

Enhancement over MAX II/V UFM
Up to 320 Mbps read bandwidth

SPI and I²C soft interfaces�supported in Quartus^® Prime s/w
Page and Sector erase support
Integrated UFM oscillator available to core

19

UFM Block

Shift Register

Data Register

DRDin

Address Register

DRCLK

DRSHFT

ARDin

ARCLK

nErase

nProgram

OSC

UFM Sector 0

UFM Sector 1

Program

Erase

Control

ARSHFT

DRDout

32

Busy

OSC

RTP_Busy

nOSC_ENA

PAR_EN

23

32

The UFM Block is an enhanced and larger version of the UFM used in MAX II and MAX V devices. The total available bit size is up to 512 Kbits and is divided into two equal size sectors. The UFM supports the same native serial interface from MAX II and MAX V devices but now also has a native 32 bit wide parallel interface for faster read access. The serial or parallel mode is controlled via the PAR_EN signal.

It supports SPI and I2C soft interfaces.

And, the maximum clock frequency supported is 116 MHz, which provides 320 Mbps of read access from the UFM to the core. This is ideal for the Nios II processor or other code storage applications.

The UFM has been further enhanced with a UFM page erase feature. The width of the page size is density dependent and at this point still TBD.

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User Flash Memory Organization

Use-Models Include Scratch-Pad

Memory for Nios II Processor Code

20

Device	Page Size (bits)	Pages / Sector	# of Sectors	Total UFM Size (bits)
10M02	16,384	3	2	98,304
10M04	16,384	8	1	131,072
10M08	16,384	8	2	262,144
10M16	32,768	4	2	262,144
10M25	32,768	4	2	262,144
10M40	65,536	4	2	524,288
10M50	65,536	4	2	524,288

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MAX 10 FPGA – Optional Integrated Linear Regulator

Option 1 – Dual Supply

Higher Performance
More Features

Option 2 – Single Supply

Simple, compact PCB
Lower BOM cost

21

MAX 10 FPGA

1.2V

2.5V

Die 1

MAX 10 FPGA

3.0 or 3.3V

1.2V

Die 2

There are two voltage variants within the MAX 10 FPGA family – Dual Supply and Single Supply. This refers to how many voltage rails need to be externally supplied to the device.
These two options represent physically different die (one base wafer, two metal mask options); you can’t flick a switch to toggle between them – you get one or the other, so the package options and ordering codes are arranged accordingly.
Option 1 is the Dual Supply option (or “classic” operation mode). In this mode, the chip requires the two separate 1.2V and 2.5V rails. These need to be sourced from the board. This situation is optimized for performance and power efficiency.
In Option 2 – the Single-Supply option, the user can take advantage of an on-chip linear regulator which converts the externally supplied 3.0 or 3.3V into the required 1.2 and 2.5V internal voltages needed for operation of the device. This option is provided as a convenience to the customer to help them optimize their PCB for lower cost, reduce the overall form-factor, or to reduce the BOM cost (fewer external power regulators needed to power the PLD).
(INTERNAL NOTES: The Single supply variant may still need another voltage regulator to supply the Vccio reference voltage needed for certain I/O standards (e.g. 2.5V for LVDS).

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�Max 10 FPGA – Power Savings

22

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Sleep Mode Capability & Ref. Design

Low power mode without losing state
External control via single pin
Wake-up from sleep in < 1 ms
Gates clocks to internal logic
Disables I/O

23

Core

Logic

Power Management Controller

(User Defined)

SLEEP / WAKE Pin

I/O

Disable

Gated Clock

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“Sleep” Mode

24

Clock Pins

Sleep / Wake Pin

5%-95% Dynamic Power Reduction

MAX 10 FPGA

Device

I/O

Customer’s State Machine

I/O Tristate Signals

I/O Tristate

Signals

I/O

Clock

Gating

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MAX10 FPGA – Core Architecture

25

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Logic Element (LE) and Interconnect

LE = 4-input Look Up Table (LUT) + Register

Two dedicated paths between LEs:

Carry chain

Chain runs the entire length of a LAB Block Column

Register cascade

Cascade chain can start & finish at any LE
Multiple chains supported
Register cascade between LAB blocks is not supported

26

LUT

Reg

LUT

Reg

Carry Chain In

Reg

Cascade In

Reg Output

LUT Inputs

Carry

Chain Out

Reg

Cascade Out

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Logic Array Block (LAB) Structure

Logic Element

Look Up Table + Register + Output Logic

Logic Array Block

16 Logic Elements
Control Block (middle of LAB)
Lab-wide routing (not shown)

27

The MAX 10 chip family also uses programmable matrix architectures similar to FPGAs. A two-dimensional row- and column-based architecture of the interconnect matrix are used in MAX 10 instead of one common matrix for communication between logical blocks for classic CPLD (MAX 7000 for example). This allows as to significantly reduce the chip size by increasing the number of logic blocks compared to the classic CPLD.

The Logic Array Block (LAB) consists of 16 Logic Elements (LE) and a LAB-wide Control Block (LCB) and LAB-wide routing resources. They are organized in columns throughout the device. The LAB-wide Control Block is physically located in the mid-section of the LAB with 8 LEs above and 8 LEs below it.

Not all the control signals or routing interconnect are shown so as not to clutter up the diagram and confuse the issue.

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MAX10 FPGA – DSP

28

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Basic DSP Architecture

Only non-volatile, low-cost FPGA with dedicated hard multipliers

Supports Up To:

144 18x18 multipliers or,
288 9x9 multipliers

Maximum multiplier performance of 310 MHz

29

Up to 288

Multipliers

DSP Blocks

Config.

Flash

User Flash

Control Block

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DSP Block Organization

Implemented as column elements in between LAB columns
Multiplications greater than 18-bits are supported via cascade chaining of DSP blocks

Supports wide multiplication

Automatically supported in Quartus® Prime software

30

Embedded

Multiplier #1

Embedded

Multiplier #n

Embedded

Multiplier

Column

LAB

Row #1

LAB

Column

#1

LAB

Column

#n

LAB

Row #n

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MAX 10 embedded DSP block

31

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DSP Performance

32

MAX 10 FPGA Supply Variant	Speed Grade
MAX 10 FPGA Supply Variant	-6	-7	-8
MAX 10D - Dual Supply	310 MHz	260 MHz	210 MHz
MAX 10S - Single Supply	198 MHz	183 MHz	160 MHz

MAX 10 FPGA Supply Variant	Speed Grade
MAX 10 FPGA Supply Variant	-6	-7	-8
MAX 10D - Dual Supply	265 MHz	240 MHz	190 MHz
MAX 10S - Single Supply	198 MHz	183 MHz	160 MHz

9 × 9-bit multiplier

18 × 18-bit multiplier

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MAX10 FPGA – Phase Locked Loops (PLLs) and Clocks

33

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Full Featured PLLs

Up to four full-featured PLLs

Five programmable outputs per PLL
Dynamically change both frequency and phase
Up to 10 global clocks and 2 external clocks outputs from 1 clock source

Flexibility

Support multiple or unknown input frequencies using dynamic reconfiguration
PLL counter cascading for finer clock synthesis resolution
Single PLL supply device option

External interface support

x16 DDR3 interfaces using a single PLL
Support for LVDS interfaces up to 830 Mbps

34

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Low Power Clocking Architecture

Low power…when needed

Dynamic enable/disable for power control/sleep
Unused networks automatically powered down

High performance

Up to 450MHz

Flexible clocking resources

Up to 20 global clock networks with dynamic user clock selection
Oscillator for Self-running applications – sleep controller, watch-dogs, etc.

35

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Max 10 FPGA – Internal Memory

36

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M9K Embedded RAM Blocks

37

Feature	M9K	Benefit
Block Size	9 Kbits	Optimizes Memory
Performance	Up to 330 MHz	Hi speed Performance
Dual-Port Read During Write Behavior	New Data or Old Data	Flexibility and �Ease of Use
Parity Bit	Yes	Usability for High Reliability Apps
Clock Enables	4	Increased Flexibility �and Reduced Power
Read and Write Enables	4	Increased Flexibility �and Reduced Power

Max 10 FPGA family

9 Kbits

18

36

or

18

36

or

M9K

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M9K Block Key features

9,216 RAM bits including parity bits

Variable port width configurations of x1, x2, x4, x8, x9, x16, x18, x32 and x36
Synchronous only operation operating up to 330 MHz
Parity support by storing one extra bit per byte in x9, x18 and x36 modes.

Data options

Byte enable support for data input masking during write
Address stall for efficiency in cache-miss applications
Same-port read-during-write to read out new data
Same-port read-during-write to read out old data

Port options

Single-port mode and simple dual-port mode supported for all port widths
True dual-port operation in x1, x2, x4, x8 x9, x16 and x18 modes
Pack mode in which 9k MEAB is split into two 4.5k single port RAMs
Mixed-port same-clock read-during-write to read out old data.

Control options

total of 4 clock enable controls.
Separate read enable and write enable for each port.
Asynchronous clear for output latches
Asynchronous clear for address registers.

ROM mode with preload supported for all port widths*

38

* Feature available depending on configuration option used.

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MAX 10 FPGAs – General Purpose I/O (GPIO)

39

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I/O Features & Benefits

40

I/O features	Benefit
Multiple interfaces, standards, and features supported	Easily bridge between different devices having different voltage levels or protocols Flexible I/O placements for easier PCB design and �to reduce board area
Large number of I/O banks	Better granularity to mix and match different I/O requirements
Abundant I/O element registers	Increase external memory interface performance Improve Tco performance
Dedicated differential �output buffers	Eliminate external resistors for LVDS, RSDS, �and mini-LVDS transmission LVDS interfaces up to 720 Mbps (preliminary)
Selectable series OCT �(some with calibration)	On-chip termination reduces external passive cost & calibration eliminates variations due to PVT
Adjustable slew rates	Improve signal integrity by slowing down edge rates on �non-performance-critical I/O pins

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I/O Bank Details

Interface to 3.3, 2.5, 1.8, 1.5, and 1.2V logic levels
3.3V PCI 32-bit, 33 MHz compatible

PCI clamp diode on all pins

Output enable per pin
Noise control features

Schmitt Triggers
Three step slew rate
Programmable output drive strength

Emulated-LVDS I/O on all banks

True LVDS I/O, bottom banks only

On-chip series termination & Hot-Socket Compliant

41

All I/O standards True LVDS Tx

All I/O standards

Bank 3

Bank 8

Bank 2

MAX 10 FPGAs

Bank 1

Bank 5

Bank 6

Bank 3

Bank 2

MAX 10 FPGAs

Bank 1

Bank 5

Bank 6

Bank 4

Bank 8

Bank 7

All I/O standards True LVDS Tx

All I/O standards

Ext. Memory I/F (10M16-50)

All I/O standards

10M02

10M04 – 10M50

The I/O can interface to a variety of different voltage levels from 1.2V up to 3.3V to accommodate a wide variety of I/O standards
The I/O are also 3.3V PCI 32-bit, 33 MHz compatible, with available PCI clamping diode on all pins
The majority of I/O pins are bidirectional in nature with noise control features, including slow slew rate control and low drive strength options.
The devices support “emulated” LVDS on all banks and “true LVDS” on the bottom banks. More details on emulated and true LVDS are discussed in the LVDS section.
On-chip series termination (OCT) is available on all devices & banks (This is used for single ended I/O termination). “Calibrated” OCT is only available on 10M16-10M50 devices, and only on banks 5 & 6.
Support for DDR3, DDR3L, DDR2, and LPDDR2 are available on the right banks but only for the 10M16, 10M25, 10M40, and 10M50 devices. Special features were added to these I/O elements to support the high speed data & clock capturing needed for EMIF timing (i.e. PHY clocks, extra I/O registers, etc.).

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MAX 10 FPGA – Internal Oscillator

42

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Integrated Oscillator Clock Source

Internal Ring Oscillator with clock multiplexers and dividers

Maximum Freq 232MHz*

Uninterruptable clock source located within the UFM

43

Ring

Oscillator

UFM

OSC_ENA

Div 32

Div 2

Int osc

*10M40/50 144MHz

Internal OSC Frequency (MHz)
Device	Min	Typ	MAX
10M02 / 04 / 08 / 16 / 25	55	82	116
10M40 / 50	35	52	77

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MAX 10 Application

44

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MAX 10 Broad Application Coverage

Industrial drives
Motor control
I/O modules

Automotive infotainment
Automotive driver assist
E-vehicle

Communications
Computing
Storage

45

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MAX 10 FPGA Industrial Applications

Drives, IO modules, industrial Ethernet, machine vision, motor control, smart energy inverters

46

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MAX 10 FPGA Applications in Motor Control

Single chip solution = Drive-on-Chip (DOC)

Targets lower-voltage, lower complexity applications than existing Cyclone V SoC DOC
Integrated ADCs reduce BOM cost in in low voltage applications

Companion Chip, next to existing microprocessor

Incremental integration of PLD into motor control (reduces risk)
Augment existing design with new features / capabilities

Minimal or no change to existing motor-control algorithms
Design remains largely in designer comfort-zone of software-based control
Potentially lower cost than having to switch microcontrollers

47

Motor controls are a major industrial application for MAX 10 FPGAs. The non-volatile, single-chip MAX 10 FPGAs provide a “drive-on-chip” solution to customers. These are lower-voltage, lower complexity drives than those targeted by CV SOC Drive-on-chip, and with an additional benefit of flash and ADC integration.

In other motor control applications, the customer may not be comfortable changing out their uC and software investment. In these cases, we can use MAX 10 as a companion chip to the microprocessor or microcontroller. This reduces design risk for the customer but puts Altera on the board and in a position to integrate more function in future generations of their design. The customer has the benefit of not changing their SW algorithms and may potential save cost by not switching to a more complex microcontroller or processor sub-system.

Examples:

Add Ethernet I/F not supported by existing µC

Add capability to drive touch-panel HMI to µC originally capable of supporting buttons and LEDs only

Add an encoder interface (quadrature decoder) not supported by existing µC

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Motor Types & Applications – Where Do �MAX 10 FPGAs Fit?

48

5V

24V

400V

x kV

Voltage

System Cost & Algorithm �Complexity

SR

DFIG

PMSM

IM

�BLDC

STEPPER

DC

DC = Direct Current

BLDC = Brushless DC

PMSM = Permanent Magnet Synchronous Motor

IM = Induction Motor

SR = Switched Reluctance Motor

DFIG = Double FET Induction Generator

[THIS SLIDE HAS BUILD]

Obviously, the first step is to understand where to position MAX10 in Motor Control.

This slide plots various types of motors on a graph bounded by system cost and complexity on the vertical axis and drive voltage on the horizontal axis.

Starting from the bottom left in voltage and complexity, we have DC motors, Stepper motors, brushless DC, Switched Reluctance motors, induction motors, permanent magnet synchronous motors, and finally Double FET induction generators.

[CLICK TO NEXT BUILD]

Superimposing some of the common applications related to those motor types, we are now ready to understand where MAX10 FPGAs fit.

[CLICK TO NEXT BUILD]

Given MAX10 FPGA features, it is most likely to fit in the region bounded between 5V to 400V motor drive and in applications like electric power steering for golf carts, washing machine drum control applications, surveillance camera pan-tilt-zoom (PTZ) and some mid-range performance factory automation equipment like low speed lathes and milling machines, conveyors and the like.

But how do we know which application and performance combination is a sweet spot for MAX10 FPGAs? We will examine a way to determine that in the next slide.

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Motor Types & Applications – Where Do �MAX 10 FPGAs Fit?

49

5V

24V

400V

x kV

Voltage

System Cost & Algorithm �Complexity

SR

DFIG

PMSM

IM

�BLDC

STEPPER

DC

DC = Direct Current

BLDC = Brushless DC

PMSM = Permanent Magnet Synchronous Motor

IM = Induction Motor

SR = Switched Reluctance Motor

DFIG = Double FET Induction Generator

Power Station Turbine Generator

Elevator

Train traction

Wind Turbine Generator

Factory Automation

EV Traction

Washing Machine Drum

Washing Machine Pump

Vacuum Cleaner

Electric Power Steering

Disk Drive Rotation

Fan

Disk drive / print head

[CLICK TO NEXT BUILD]

Superimposing some of the common applications related to those motor types, we are now ready to understand where MAX10 FPGAs fit. These include washing machine pumps and drums, vacuum cleaners, electric power steering, factory automation and many other areas across the motor spectrum.

[CLICK TO NEXT BUILD]

Given MAX10 FPGA features, it is most likely to fit in the region bounded between 5V to 400V motor drive and in applications like electric power steering for golf carts, washing machine drum control applications, surveillance camera pan-tilt-zoom (PTZ) and some mid-range performance factory automation equipment like low speed lathes and milling machines, conveyors and the like.

But how do we know which application and performance combination is a sweet spot for MAX10 FPGAs? We will examine a way to determine that in the next slide.

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Motor Types & Applications – Where Do �MAX 10 FPGAs Fit?

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5V

24V

400V

x kV

Voltage

System Cost & Algorithm �Complexity

SR

DFIG

PMSM

IM

�BLDC

STEPPER

DC

DC = Direct Current

BLDC = Brushless DC

PMSM = Permanent Magnet Synchronous Motor

IM = Induction Motor

SR = Switched Reluctance Motor

DFIG = Double FET Induction Generator

Power Station Turbine Generator

Elevator

Train traction

Wind Turbine Generator

Factory Automation

EV Traction

Washing Machine Drum

Washing Machine Pump

Vacuum Cleaner

Electric Power Steering

Disk Drive Rotation

Fan

Disk drive / print head

REGION OF

MAX10 TARGETS

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What Additional Drives Markets do MAX 10 FPGAs Enable?

High end motors already well serviced by CV SoC
MAX 10 FPGA targets mid range motor control market
Low end market is super low cost = MCU domain

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50% of Motor Control Applications

20%

of

Motor

Control Applications

30% of

Motor Control Applications

CPU Performance Equivalent

1.8 GHz

500 MHz

350 MHz

HIGH-END

MID-RANGE

LOW-END

Motor Control Spectrum

In this slide we take our motor types and applications graph from the previous slide and expand it with the motor control performance pyramid. This divides the motor control applications by performance into low-end, mid-range and high-end categories. To choose an understandable measure, we have used the applications’ required CPU-Performance-Equivalent to make this division. These numbers are not cast in stone, and everyone’s idea of the cut-off points may differ, but it does serve as a guideline as to where to position MAX10 in motor control and where to position something else or, perhaps, to just stay away, since competing may be a challenge.

One thing is for sure: a very large percentage of motor control apps are the domain of the sub-1-dollar microcontroller. Traditionally where FPGAs have done well is in the space represented from the upper end of the mid-range to the top of the high-end. Here, FPGAs – and especially SoC FPGAs, provide performance benefits that microcontroller and DSP find hard to match at a reasonable cost.

MAX10 enables you to move the game into the space between the low-end and the high-end, expanding our sockets down the pyramid of motor control applications.

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MAX10 Design Example�Other Industrial Applications (1)

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Industrial Ethernet Switch

Fieldbus Buffer/Bridge

MAX 10 FPGA value = Single Chip Programmable

As with drive on a chip, unique combinations of IP can be combined on a single MAX10 to implement other industrial solutions on a single device.

The above examples include an industrial Ethernet switch with IEEE1588 synchronization or a fieldbus buffer bridge.

The Ethernet switch might be standard Ethernet, or one or more of the many Industrial Ethernet protocols available from Altera’s IP partners (e.g. EtherCAT, ProfiNet, Ethernet IP, and POWERLINK). This design would involve one of the larger MAX10s available. The user flash might be used for a number of applications including operational parameters.

The Fieldbus Buffer/Bridge product could support any combination of fieldbuses that could be changed dynamically. This simple design could be supported in a smaller to mid-range density MAX10.

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MAX10 Design Example�Other Industrial Applications (2)

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HMI Controller

Remote Power Meter

MAX 10 FPGA value = Single Chip Programmable & ADC

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MAX10 Design Example�Other Industrial Applications (3)

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Inverter

MAX 10 FPGA value = Single Chip + ADC

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MAX 10 as Board Management Controller

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System Management Tasks and Functions

Power Rail Management

Start up
Configure
Maintain
Power down

Thermal Management

Monitor thermal environment
Evaluate environment data
Mitigate conditions or initiate damage prevention

Diagnostics / Prognostics

Record events
Analyze data log
Predict failure

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Power Rail Management Functions

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Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion

Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion
Power On	Main power supply on and stable Power tree not initialized	Monitor line-side power stability Avoid brownout conditions

Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion
Power On	Main power supply on and stable Power tree not initialized	Monitor line-side power stability Avoid brownout conditions
Power Up	Power rails initialized: in prescribed sequence at prescribed ramp rate	Out of sequence rails can cause: high power consumption unstable operation reduce operating life device damage

Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion
Power On	Main power supply on and stable Power tree not initialized	Monitor line-side power stability Avoid brownout conditions
Power Up	Power rails initialized: in prescribed sequence at prescribed ramp rate	Out of sequence rails can cause: high power consumption unstable operation reduce operating life device damage
Run time	Maintain power rail voltage and current Communicate system health	Power rail drift and fluctuation can: put devices into unknown or unstable states undetected, reduce system reliability

Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion
Power On	Main power supply on and stable Power tree not initialized	Monitor line-side power stability Avoid brownout conditions
Power Up	Power rails initialized: in prescribed sequence at prescribed ramp rate	Out of sequence rails can cause: high power consumption unstable operation reduce operating life device damage
Run time	Maintain power rail voltage and current Communicate system health	Power rail drift and fluctuation can: put devices into unknown or unstable states undetected, reduce system reliability
Low-power / Sleep Option	Turn down / turn off system blocks: reduce power consumption reduce cooling / operating costs	Low-power / sleep states: need specific voltage sequencing and control depending on desired state

Power State	Description	Key Design Considerations
Off	No power applied.	Hot-socketing support: Initialize upon insertion
Power On	Main power supply on and stable Power tree not initialized	Monitor line-side power stability Avoid brownout conditions
Power Up	Power rails initialized: in prescribed sequence at prescribed ramp rate	Out of sequence rails can cause: high power consumption unstable operation reduce operating life device damage
Run time	Maintain power rail voltage and current Communicate system health	Power rail drift and fluctuation can: put devices into unknown or unstable states undetected, reduce system reliability
Low-power / Sleep Option	Turn down / turn off system blocks: reduce power consumption reduce cooling / operating costs	Low-power / sleep states: need specific voltage sequencing and control depending on desired state
Power Down	Power rails powered down: in prescribed sequence	Uncontrolled power down can create: internal potential differences reducing device operational life

Power State	Description	Key Design Considerations

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MAX 10 FPGA Automotive Applications

Infotainment, Radar, ADAS, E-Vehicle

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Automotive Infotainment Application:�Interface / Video Function & Timing Controller

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LCD

960 x 540p60

Video Source

GPU / SoC

Small footprint with FLASH & ADC integration

The right IO and IP from Altera make MAX10

Ideal for Display Driving TCON applications

MAX10

OpenLDI

miniLVDS

VIP

Suite

TCON

Logic

CFIG

GPIO

Safety

4D+C LVDS�Open LDI

12D+2C �miniLVDS

IO Support: LVDS inputs, mini-LVDS outputs, and LVCMOS GPIOs

Altera IP: ALTLVDS MegaFunction, and VIP Suite

MAX10 FPGA: granular family, on-chip FLASH for reduced BOM

40MHz/280Mbps x4�(1.12Gbps)

10M02D

10M04D

1.2V/2.5V and VDDIO

Here is a MAX10 FPGA in a display driver infotainment application. This could be for a Instrument Cluster, Center Stack or Rear Seat Entertainment Display. The MAX10 is used between the video source / GPU device and the LCD. It performs multiple functions including: Interface bridging – the conversion of OpenLDI (LVDS) to miniLVDS, video functions such as scaling or other graphical enhancements, and also TCON (aka Timing Controller) where column driver data and LCD control signals are generated from the received pixels and video timing (DE, VS, HS, and PCLK).

MAX10 is superior over other solutions due to its granular family offerings – the right size device for the application and its on-chip FLASH feature which eliminates the need for the external config device for reduced BOM. The on-chip ADC and temp sensing diode can be utilized to read out local temperature which may be monitored for heat from back lights.

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Automotive ADAS Application – MAX10:�Radar Processing Acceleration

Performance to achieve high level of processing bandwidth through parallelism

1.2 Tbits of memory bandwidth, >25GMACs
Implement CA & OS CFAR parallel processing
25ms radar processing time

Enhanced safety with BIST on every radar frame
Fast TTM and balanced TCO using high-level design flow and tools

Low System BOM due to integrated Configuration Flash
MCU choice decoupled from Radar processing performance
Flexible Package Options
Complementary, small footprint integrated power solutions

Lower System Costs
Scalable Performance
Small footprint

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MAX10�FPGA Subsystem

Enpirion Power Supply Subsystem

Low-cost�ASIL-D MCU

ADC I/O

CAN

FlexRay

SPI* or other I/F per MCU

MAX 10 FPGA Companion Value

5V

Here is a MAX10 FPGA in a Hardware Accelerator application in Automotive RADAR. MAX 10 can process a vast amount of radar data quickly and provide high throughput memory access needed by the application. An MCU alone would struggle to keep up with this data challenge. In this solution, a low-cost MCU can be used for the system interface and safety monitoring complimenting the high performance parallel processing of the FPGA. Altera’s Enpirion power supply is also used for local high efficiency power rail generation in a compact footprint. The integration of FLASH also eliminates the need for an external configuration device all helping to make this a small footprint ECU.

Typically, Radar processing needs to occur in less than 40ms, in this example, the MAX10 estimate is just 25ms. The flexibility of the FPGA allows for BIST (Built in Self Test) and diagnostic blocks to be deployed in each frame.

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MAX 10 FPGA ADAS Radar Subsystem Detail

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FFT

Complex Scalar

Acc.

CFAR

Acc.

Fast ADCs

14Bit

10-50Msps

LVDS (6-12ch)

320Mbps

10M50DA

SPI slave

Max10 User flash (NV data)

64KB

SPI slave

SPI controller

Assumptions:

Flash/RAM requirements met by MCU

Notes:

Additional SPI slave shown to access Flash for data storage.
Optional Ethernet capability shown. May require dedicated SPI link dependent on BW.
Data on SPI link must be protected with CRC.

Ethernet MAC

or

Ethernet AVB endpoint

12 bit ADC with temp sensor

Ethernet / BRR PHY

1Mx36

SRAM

External device

Soft IP

Hard IP

Key:

78

4x LVDS pairs / channel

SRAM controller

Optional IO expansion

ASIL-D Lockstepped Automotive MCU

96

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Why Use Programmable Logic for Consumer?

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PLD Benefits	Functions (Most Popular Uses)
Design Flexibility	Protocol or Interface Bridging
Reprogrammable	Voltage Level Shifting
Remote update, reduces Field Service $	GPIO Expansion
Instant “On” (non-volatile)	Data Format Converter
Content and/or IP Protection	Image Enhancement, Overlays, etc.
Small Package Sizes (or bare die)	Audio Enhancement
	Timing Controller
-	Flash/DDR Controller
-	Power Management
-	Power-up Sequencing
-	Security Monitor / Manager
-	System Configuration

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Consumer functions: Simple 🡪 Complex

63

Image co-processor

I/O Expansion

Motor control

3

10’s – 100’s

I/Os

CPLD

or FPGA

PWM

FPGA

or CPLD

Processor

Display

I/F

Video overlays,

enhancements,

LCD driver, etc.

Bridging

I²C

SPI

ASSP

ASIC

CPLD

or FPGA

FPGA

or CPLD

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Summary

MAX 10 FPGAs’ largest obtainable markets are Industrial, Automotive, and Communications
MAX 10 FPGAs target many areas of Industrial including motor control, Industrial Ethernet, HMI, and PV inverters
MAX 10 FPGAs target many areas in Automotive including infotainment, radar, V2X, and e-vehicle
MAX 10 FPGAs provide higher density and capabilities for control applications in Comms, Computer/Storage, and Consumer

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Thank you!

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