Toy CGRA Final Presentation

Charles Tsao and Po-Han Chen

Outline

• Background
• AHA Project Introduction
• CGRA Architecture
• Chip Bring-up
• Top-level Chip Interface
• SoC Test
• Configuration Test
• IO Test / Full Test
• Measurement

Why Do We Need CGRA?

AHA: Agile Hardware Design Flow Using CGRA

• CGRA generation : quickly creates a CGRA
• Application mapping : accelerates dense linear algebra applications on the CGRA

CGRA Architecture

P

M

M

M

P

P

P

P

P

Switch Box

Connection Box

Processing Element Core

Memory Core

5

Processing Element Core

6

Memory Core

Dual-Port Wide-Fetch (2) SRAM

With Static Scheduling Controllers

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Toy CGRA Architecture

configuration bitstream

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Toy CGRA Architecture

configuration bitstream

9

Physical Design Results

Top-Level Block Diagram

reference: https://github.com/efabless/caravel

User Project Area

• 34 GPIO pins can be configured as input/output in mgmt C code

​

• 32 bits of config data are driven by wishbone�
• 32 bits of config address are driven by wishbone�
• CGRA stall driven by wishbone

​

• Configure input clk and rst to come from IO or WB using logic analyzer port�
• Reading out config data or message for debugging driven by wishbone

Top-Level WB, LA Connections

wbs_req = wbs_cyc_i && wbs_stb_i

wbs_wen = !wbs_ack_o && wbs_we_i && wbs_req

wbs_ren = !wbs_ack_o && !wbs_we_i && wbs_req

is_addr = wbs_adr_i == ADDR

is_wdata = wbs_adr_i == WRITE_DATA

is_rdata = wbs_adr_i == READ_DATA

stall = wbs_adr_i == STALL

​

User Project Area

wbs_dat_i

wbs_wen && is_addr

config_addr

config_wen

addr_reg

CGRA

config_ren

wbs_wen && is_wen

wbs_ren &&

is_ren

wbs_dat_i[0]

wbs_dat_i[0]

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PicoRV32 Software Interface

• Using caravel board firmware from efabless to control mgmt area with C code
• Cross-compiled and flashed onto PicoRV32

​

​

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Testing Setup

• RISC-V GNU toolchain, PicoRV32 firmware, and caravel_board firmware installed on Ubuntu Linux

​

• Board is powered and flashed from micro-USB

​

• io[6] used for outputting to serial display

​

• Chip frequently stopped working
• Mgmt SoC would hang when trying to communicate with CGRA
• revived by brushing with paintbrush and heating with hairdryer
• Suspect a hold time violation (?)

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SoC Bringup Test

• Simple C test to gain familiarity with system
• Prints msg on a serial display using a while loop

​

15

Configuration Test

• Successfully tested write to all configuration registers and write to SRAM macro

​

• Test spans 6 different configurations due to only 2kb memory on PicoRV32
• 1000 registers each

​

• Not all 32 bits of register are always used
• Range given by hi and lo
• encode write
• decode read

​

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IO Test + Full Test

• FPGA used to toggle GPIO�
• 2 pmods used for toggling 10 IO signals for initial test

​

• LPC FMC breakout board used to toggle all 34 IO signals

​

• Currently mgmt area hangs when trying to communicate with CGRA

​

• Full test: configured conv_3_3 bitstream but because of above could not verify

​

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Future Work

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Limitations

• Array is small, can only run tiny applications�
• Maximum clock frequency of 50 MHz limited by GPIO
• should have implemented a global buffer�
• Configuration depends on harness SoC
• should have created a bypass path�
• Testing requires significant effort in setting up FPGA and �application toolchain
• should have a built-in pixel generating circuits to enable self-testing

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Key Contributions and Takeaways

• First chip that validates the technology portability of agile hardware design flow

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• Can accelerate more than one application on this chip

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• Helped improve open-source toolchains by debugging with efabless

​

• Learned a lot, but slow iteration due to lack of experience and limited time

​

• Should’ve created backup methods for testing

Enabled following year’s EE372 students to suffer less :’)

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Toy CGRA Backup Slides

Charles Tsao and Po-Han Chen

Application Flow

Software

Hardware

tbg.py / fault

Caravel SoC (FPGA, C mgmt)

Interconnect_tb.sv

garnet.v

xcelium

Output comparison

CGRA

Output comparison

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Physical Design Results (PE)

650 nm

180 nm

Physical Design Results (MEM)

650 nm

800 nm

Physical Design Results (Whole array layout)

SB in

SB out

passthrough

Physical Design Results (Whole array)

Outline

• Motivation, CGRA Introduction
• Block Diagrams
• High-level DSLs
• Interconnects
• PE Tile Architecture
• Area and performance estimates
• Memory Tile Architecture
• Area and performance estimates
• Application Dataflow
• Verification and Evaluation
• Future Tasks

Motivation

General Purpose

Processor

Specialized

Accelerator

CPU

ASIC

EE272A

Resnet-18

Accelerator

AMD

Ryzen 5800X

CGRA

Stanford AHA

Garnet

FPGA

Xilinx

Virtex-7

General purpose processor versus Specialized accelerator

Energy Efficiency

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Motivation

General Purpose

Processor

Specialized

Accelerator

CPU

ASIC

EE272A

Resnet-18

Accelerator

AMD

Ryzen 5800X

CGRA

Stanford AHA

Garnet

FPGA

Xilinx

Virtex-7

• CGRA that can accelerate a variety of image processing applications
• Specifically, Convolutional Neural Networks

Energy Efficiency

EE272B

Toy

CGRA

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General CGRA Architecture

• Tile_PE
• PE Unit
• Interconnects
• Connection Boxes
• Switch Boxes
• Tile_MemCore
• Memory Units (SRAM, reg)
• Interconnects
• Connection Boxes
• Switch Boxes
• Tile_IO_core
• Connects 16 bit and 1 bit inputs to leftmost tiles

IO

IO

IO

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High Level DSLs

• Our CGRA hardware is implemented using 3 pythonic hardware DSLs:
• PEak for PEs
• Lake for Memories
• Canal for Interconnects

​

• Each specification serves as a single source of truth
• Verify design functionally
• Verify design hardware
• Generate rewrite rules from CoreIR for mapper

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High Level DSLs

• Our CGRA hardware is implemented using 3 hardware DSLs:
• PEak for PEs
• Lake for Memories
• Canal for Interconnects

​

• Each specification serves as a single source of truth
• Verify design functionally
• Verify design hardware
• Generate rewrite rules from CoreIR for mapper

​

• Halide: high-level language for applications to map and run on CGRA

32

Toy CGRA Architecture

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Top-Level Block Diagram

reference: https://github.com/efabless/caravel

User Project Area

• 34 Input and output IO tiles are driven by the 38 GPIO pads�
• 32 bits of config data are driven by wishbone�
• 32 bits of config address are driven by wishbone�
• Stall driven by remaining IO or logic analyzer ports�
• Reading out config data for debugging driven by wishbone

Interconnects

• Connection Boxes feed inputs into the PE
• 5 connection box modules in Tile_PE and Tile_MemCore
• Three 1 bit inputs
• Two 16 bit inputs�
• Switch Boxes route outputs to CB or out of accelerator
• 2 switch box modules in Tile_PE and Tile_MemCore
• 1 bit
• 16 bit

​

• Routes are configured through bitstream (which is input into configuration ports)

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Baseline PE Tile

4 tiles

10 tiles

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PE Architecture (with LUT)

• Input data comes from two 16b CBs�
• Bit input Data three 1b CBs�
• Muxes in green can be configured for direct connection or pipelined input�
• Cond used for condition codes
• (e.g. zero, overflow, negative, etc.)�
• Look up table - like FPGA

​

• Output goes to switch box

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PE Architecture (optimized)

• Input data comes from two 16b CBs�
• Bit input Data three 1b CBs�
• Muxes in green can be configured for direct connection or pipelined input�
• Cond used for condition codes
• (e.g. zero, overflow, negative, etc.)

​

• Look up table - like FPGA

​

• Output goes to switch box

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PE Tile - Area Distribution

PE Tile

Main components:

• PE
• Switch Boxes

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Memory Tile

• Programmable access patterns
• High level for-loop description → low level access address/schedule

Compiler

Tool Chain

Configuration

Bitstream

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Memory Tile

• Programmable access patterns
• High level for-loop description → low level access address/schedule

Compiler

Tool Chain

Configuration

Bitstream

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Memory Tile - Architecture

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Memory Tile - Wide Memory

• Wide memory → reduce memory access energy (nJ/bit)

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Memory Tile - Area Distribution

Memory Tile

Main components:

• Address/Scheduling Controls
• Config Registers
• 2 Dual-port Memory Macros

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Chip Physical Layout and Spec

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Application Flow

Software

tbg.py / fault

Interconnect_tb.sv

garnet.v

xcelium

Output comparison

CGRA

Output comparison

Toggle IO w/ FPGA

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Verification

• Unit Tests
• PE Tile
• Memory Tile
• Applications (Verified)
• Pointwise Brightening
• Gaussian Blurring
• 2D convolution of various kernel sizes
• 1x1, 2x2, 3x3...
• Applications (Constructing)
• Resnet
• Mobilenet
• VGG
• Testibility
• Config circuitry supports read-back check

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