Chisel Bootcamp

Hands on workshop on “Creating a

RISC V microcontroller using Chisel”

Outline

• RISC-V ?
• Getting Started with RISC-V?
• Chisel Framework
• Environment Setup
• Chisel Introduction
• Chisel Examples

​

​

RISC-V

01

“Risk-five” , an Open Source instruction set, and a lot more….

​

• Open , but Frozen, ISA
• Developed by Academic Community, UC Berkeley in 2010
• Open to Customization
• Clean State Design, No over architecturing
• RISC V Foundation

Getting Started

02

--

​

• GitHub : https://github.com/riscv/riscv-cores-list
• FE310 - SOC
• ICE40, Arty - Evaluation
• Generators : Chisel, Bluespec.

Chisel Framework

03

Open Source Tools to generate Hardware Description.

1

Let’s start…..

Get equipped

https://gitlab.com/icfoss/openfpga/chisel-bootcamp/workshop/-/blob/master/README.md

What is chisel?

A powerful, highly abstract, HDL based on Scala

​

The complete power of Scala in an HDL

​

Why chisel?

​

Hopefully you’ll be able to answer that by the end of the session….

​

Basic Setup of a chisel project

Go ahead and clone the repo… make sure to change the name to one of your liking

https://github.com/freechipsproject /chisel-template.git

​

De-initialize the git repo

$ rm -rf .git

$git init

$git add .gitignore ./

Be wary of the differences

Chisel is an HDL and not a programming language.

​

Everything is hardware.

Data types

1. Bool- Analogous to Boolean but represents the state a wire can take
2. UInt-Analogous to conventional uint but represents a collection of Bools
3. SInt- The signed version of UInt

Exercise 1

Create a simple wire through module. What goes in comes out…..

Introduction to conventions, wires and the := operator, and testing

Exercise 2

Create a delayed version of the previous exercise….Why? You’ll see…..

​

Introduction to the concept of Registers

Exercise 3

A single bit adder

​

Introduction to the Combinational Logic

Exercise 4

Ripple Carry Adder

​

Introduction to the Combinational Logic

Exercise 5

Adder/multiplier

​

Create your own adder / multiplier

Exercise 6

A Combinational Logic circuit:

​

Create your own 2 bit MUX

Exercise 7

Extend the MUX to 4 bits

Introduction to the Mux available in chisel

Exercise 8

Encoder (4x2)

Exercise 9

Decoder (4x2)

Exercise 10

Simple Packet Router

​

Introduction to the When statement

Simple router

Data

Rank info

High p channel

Low p channel

default

Exercise 11

Counter

Given what you’ve learnt so far, write your own counter

Exercise 12

Introduction to state machines:

​

The classic vending machine problem

Exercise 13

Packet Router

Given what you’ve learnt so far, write your own Packet router. Find the topology.