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CapTune-LO

Team A5: Charlie Chen, Jim Guo, Ethan Hu

18-500 Capstone Design, Spring 2026

Electrical and Computer Engineering Department

Carnegie Mellon University

Introduction:

Student chip fabrication labs, from university fabs like HackerFab to emerging DIY semiconductor communities, lack standardized bring-up and measurement workflows for custom-fabricated devices. Without a validated on-chip oscillator as a baseline reference, teams face time-consuming, inconsistent characterization iterations with no documented path forward for future builders.

CapTune-LO addresses this gap: we designed, fabricated, and characterized an NMOS astable multivibrator oscillator through HackerFab, supported by a custom 45×55 mm demo PCB and a repeatable, well-documented bring-up and validation workflow intended as a reusable reference for future student fabricators.

Critical Use-case Requirements:

The chip must produce sustained, observable oscillation with an output frequency tuneable across a target range by physically swapping off-chip timing capacitors. Device characteristics including threshold voltage, transconductance, and on-chip resistance must be repeatable across fabricated dies within the HackerFab conventional process tolerance, confirming that the design is robust to process variation and not a one-off result. Finally, the project must produce a documented bring-up and characterization workflow that future student fabricators can follow independently.

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Use-case Results:

The Barkhausen oscillation criterion is analytically satisfied in current devices (V2, V3), confirming the chip supports sustained oscillation behavior. Process repeatability and consistency are confirmed across more than 5 devices per iteration with device parameters within ±15% variance (standard HackerFab range). Oscillation frequency output at 1–10 kHz via off-chip cap swap is pending final oscilloscope verification on the assembled PCB. A complete bring-up and characterization workflow has been documented for future fabricators, including videos streamlining the entire fabrication and characterization process.

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ECE Areas: Hardware Systems · Circuits · Device Science & Nano-fabrication

Fig. 2: Microscope view of the fabricated on-chip oscillator with labeled pads

The fabricated die implements an NMOS astable multivibrator topology, with two cross-coupled transistors TR1/TR2 and four polysilicon pull-up resistors R1–R4 integrated through the HackerFab NMOS process. Large aluminum contact pads expose key electrical nodes (gates, drains, VDD, and VSS) for direct characterization, enabling extraction of device parameters across fabricated die iterations. The die is packaged in a PLCC-28 chip carrier and seated in the SMD socket on the demo PCB, which provides regulated power delivery, swappable timing capacitors, and MOSFET-buffered LED outputs

website: https://course.ece.cmu.edu/~ece500/projects/s26-teama5/

Fig. 3: 3-D view of the 45×55 mm CapTune-LO demo PCB

The PCB builds on a PLCC-28 SMD socket (U1) that accepts the fabricated chip carrier, with a MicroFit connector (J1) and MT3608 boost module delivering regulated 10V to the VDD rail. Swappable off-chip timing capacitors C1–C4 set oscillation frequency by setting the RC charge/discharge time constant in the cross-coupled gate paths (physically swapping capacitor values directly tunes frequency). Decoupling capacitors C5/C6 stabilize the VDD rail at the chip pins, MOSFET-buffered LEDs (Q1/Q2) provide visible Q, Q̄ output monitoring, and through-hole test points expose all key signal nodes for oscilloscope access.

Fig. 1: CapTune-LO full system diagram

A custom NMOS astable multivibrator oscillator chip (TR1/TR2), fabricated through HackerFab, is mounted on a 45×55 mm demo PCB. On-chip pull-up resistors R1–R4 and cross-coupled timing paths drive sustained oscillation; off-chip capacitors C1–C4 are physically swapped to tune output frequency (f ≈ 1/2RC). The demo PCB provides regulated 10V power (J1 + MT3608), decoupling (C5/C6), MOSFET-buffered LED indicators (Q1/Q2), and probe-accessible test points (TP3–TP6) for oscilloscope testing.

Prior to fabrication, reference NMOS device characterization was conducted to establish baseline transconductance behavior: Fig. 4 shows the key trade-off: increasing device W/L raises g_m, but at the cost of larger die area. This empirically motivated our geometry selection to satisfy the Barkhausen criterion. Post-fabrication probe-station measurements validated the design across iterations; earlier iterations failed the criterion due to routing errors and insufficient W/L, while subsequent corrections to both raised g_m to 0.94 mS with all on-chip resistances above 1500 Ω, satisfying g_m·R > 1 as confirmed in Fig. 5. Table 1 summarizes that all use-case requirements are met or analytically confirmed.

CapTune-LO demonstrated that a functional NMOS astable multivibrator oscillator can be designed, fabricated, and characterized through a student fab process. The Barkhausen criterion was achieved through targeted device W/L geometry increases and routing corrections across iterations, validating that the HackerFab process can support oscillator-class circuits when design parameters are tuned to process constraints. The off-chip capacitor architecture, initially a fab limitation, proved to be a practical feature enabling tuneable oscillation frequency without on-chip modifications.

As a team, our key lessons were that fab constraints must be confirmed before topology is finalized, that small layout errors can have outsized electrical impact, and that multi-pin probe-station measurements are far more time-intensive than anticipated. We found that iterative characterization requires significant coordination and precision during probing, and was often the main source of delay.

Looking forward, the most promising directions for continuation would be bringing timing capacitors on-chip once the HackerFab process matures, improving oxide quality to reduce gate leakage, and expanding the characterization workflow into a standardized bring-up reference that future student fabricators can follow from day one.

Table 1: Use-Case Design Requirements Validation

TR2 Drain

VDD

R2

R1

R4

R3

VSS/GND

TR1 Drain

TR1 Gate

TR2 Gate

Fig. 5: I_D–V_GS transfer characteristics for TR1 and TR2 on sample device

Fig. 4: g_m vs. device geometry: larger W/L drives higher transconductance

Power Connector

Power Decoupling Capacitors (C5, C6)

NMOS-Buffered Q LED-Indicator

NMOS-Buffered Q̄ LED-Indicator

Q Timing Capacitors (C1, C2)

Q̄ Timing Capacitors (C3, C4)