CHAPTER # 4
BASIC COMBINATIONAL CIRCUITS
INTRODUCTION
▶ Logic circuits can be broadly classified into
🡪 Combinational logic circuits
🡪 Sequential logic circuits
▶ In SEQUENTIAL CIRCUIT, there is a memory element in addition to
the logic gates.
▶ Output depends on the past condition of the output in addition to the
input at that instant.
DESIGN PROCEDURE OF COMBINATIONAL LOGIC CIRCUITS
▶ Following are the design steps of the combinational logic circuits.
HALF ADDER
LOGIC CIRCUIT OF HALF ADDER
EXPRESSION OF HALF ADDER FROM K-MAP
HALF ADDER CIRCUIT USING A-O-I GATES
HALF ADDER CIRCUIT USING NAND GATES ONLY
HALF ADDER CIRCUIT USING NOR GATES ONLY
LIMITATION OF HALF ADDER
▶ Half adders have no scope of adding the carry bit resulting from the addition of previous bits.
▶ This is a major drawback of half adders.
▶ This is because real time scenarios involve adding the multiple number of bits
which can not be accomplished using half adders.
FULL ADDER
FULL ADDER USING TWO HALF ADDERS
TRUTH TABLE & EXPRESSION
DERIVING EXPRESSION
▶ Another way of deriving carry expression
LOGIC CIRCUIT OF FULL ADDER
EXPRESSION OF FULL ADDER FROM K-MAP
FULL ADDER USING A-O-I GATES
FULL ADDER USING NAND GATES ONLY
FULL ADDER USING NOR GATES ONLY
COMPARING HALF ADDER & FULL ADDER
HALF ADDER | FULL ADDER |
1. Used for 1 bit addition | 1. Used for multi-bit addition |
2. One EX-OR gate & one AND gate are used. | 2. Two EX-OR gates, two AND gates & one OR gate are used/ One EX-OR, three AND gates & one OR gate. |
3. Output is the sum of two signals. | 3. Output is the sum of three signals. |
4. Circuit is simple. | 4. Circuit is complicated. |
5. There are two input & two output terminals. | 5.There are three input & two output terminals. |
6. It cannot be used as full adder. | 5. It can be used as half adder. |
4-BIT PARALLEL BINARY ADDER
▶ A binary parallel adder is a digital circuit that adds two binary numbers in parallel form and produces the arithmetic sum of those numbers in parallel form.
▶ It consists of full adders connected in a chain , with the output carry from each full-adder connected to the input carry of the next full-adder in the chain.
▶ The interconnection of four full-adder (FA) circuits to provide a 4-bit parallel
adder.
▶ The augends bits of A and addend bits of B are designated by subscript numbers from right to left, with subscript 0 or 1 denoting the lower –order bit.
▶ The carries are connected in a chain through the full-adders.
▶ The input carry to the adder is Cin and the output carry is C3.
▶ The S output generates the required sum bits.
IC 7483 4-BIT PARALLEL BINARY ADDER
HALF SUBTRACTOR
▶ A Half-subtractor is a combinational circuit that subtracts one bit from the
other and produces the difference.
▶ It also has an output to specify if a 1 has been borrowed.
▶ It is used to subtract the LSB of the subtrahend from the LSB of the minuend
when one binary number is subtracted from the other.
▶ A Half-subtractor is a combinational circuit with two inputs A and B and two outputs d and b. d indicates the difference and b is the output signal generated that informs the next stage that a 1 has been borrowed.
LOGIC CIRCUIT OF HALF SUBTRACTOR
EXPRESSION OF HALF SUBTRACTOR FROM K-MAP
HALF SUBTRACTOR CIRCUIT USING A-O-I GATES
HALF SUBTRACTOR CIRCUIT USING NAND GATES
HALF SUBTRACTOR CIRCUIT USING NOR GATES
FULL SUBTRACTOR
▶ The half-subtractor can be only for LSB subtraction.
▶ IF there is a borrow during the subtraction of the LSBs, it affects the subtraction in the next higher column; the subtrahend bit is subtracted from the minuend bit, considering the borrow from that column used for the subtraction in the preceding column.
▶ Such a subtraction is performed by a full-subtractor. It subtracts one bit (B) from another bit (A) , when already there is a borrow bi from this column for the subtraction in the preceding column, and outputs the difference bit (d) and the borrow bit(b) required from the next d and b.
▶ The two outputs present the difference and output borrow.
▶ The 1s and 0s for the output variables are determined from the subtraction of A-B-bi.
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR
TRUTH TABLE & EXPRESSION
DERIVING EXPRESSION
▶ Another derivation of borrow (b)
LOGIC CIRCUIT OF FULL SUBTRACTOR
EXPRESSION FOR FULL SUBTRACTION USING K-MAP
FULL SUBTRACTOR USING A-O-I GATES
FULL SUBTRACTOR USING NAND GATES
FULL SUBTRACTOR USING NOR GATES
4-BIT PARALLEL BINARY SUBTRACTOR
▶ To perform the subtraction of binary numbers with more than one bit is
performed through the parallel subtractors.
▶ This parallel subtractor can be designed in several ways, including combination of half and full subtractors, all full subtractors, all full adders with subtrahend complement input, etc.
▶ The below figure shows a 4 bit parallel binary subtractor formed by
connecting one half subtractor and three full subtractors.
▶ The subtraction of binary numbers can be carried out most conveniently by means of complements , the subtraction A-B can be done by taking the 2‘s complement of B and adding it to A .
▶ The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to the least significant pair of bits. The 1‘s complement can be implemented with inverters
COMPARATORS
▶ A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to find out whether one binary number is equal, less than or greater than the other binary number.
▶ We logically design a circuit for which we will have two inputs one for A and
other for B and have three output terminals, one for A > B condition, one for A
= B condition and one for A < B condition.
1-BIT MAGNITUDE COMPARATOR
▶ A comparator used to compare two bits is called a single bit comparator.
▶ It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.
▶ 1-bit comparator can be implemented using an EX-NOR gate, two AND gates
and two NOT gates.
TRUTH-TABLE & BOOLEAN EXPRESSION
LOGIC CIRCUIT
K-MAP
2-BIT MAGNITUDE COMPARATOR
▶ A comparator used to compare two binary numbers each of two bits is called
a 2-bit Magnitude comparator.
▶ It consists of four inputs and three outputs to generate less than, equal to and
greater than between two binary numbers.
TRUTH TABLE
BOOLEAN EXPRESSION
LOGIC CIRCUIT
K-MAP
DECODER
▶ A decoder is a logic circuit which converts n bit binary input data into 2n output lines in such a way that only one particular output line is activated for one possible combination of the input.
▶ So the number of output lines will be more than that of the input.
2 TO 4 DECODER
▶ It has 2 input and 4 output lines.
▶ Out of 4 output lines, the particular line goes to logic 1 (or logic 0) for one of the four possible combinations of the inputs A & B.
TRUTH TABLE
LOGIC GATE & BOOLEAN EXPRESSION
3 TO 8 DECODER (BINARY TO OCTAL DECODER)
▶ It has 3 input lines and eight output lines.
▶ The three input lines are A,B,C and output lines are D0 to D7.
TRUTH TABLE
LOGIC GATE & BOOLEAN EXPRESSION
APPLICATIONS OF DECODER
▶ It is used to convert the binary count into decimal digit in decade counter.
▶ Used in analog to digital converters.
▶ Used in computer and microprocessor for activating the address code of memory location.
▶ Used in output devices like printer, modem, scanner, disc drive of the computer systems.
ENCODER
▶ Function of Encoder is opposite to that of the decoder.
▶ A decoder converts the binary number into digital systems, whereas an
encoder converts decimal signal into equivalent binary signal.
▶ Encoder is a combinational logic circuit which converts the active input signal
into coded output signal.
▶ There are 2n input lines and n output lines.
▶ Number of n is less than 2n.
4 TO 2 ENCODER
▶ The 4 to 2 Encoder consists of four inputs D0, D1, D2 & D3 and two outputs
Y0 & Y1.
▶ At any time, only one of these 4 inputs can be ‘1’ in order to get the
respective binary code at the output.
TRUTH TABLE
LOGIC CIRCUIT & BOOLEAN EXPRESSION
8 TO 3 ENCODER (OCTAL TO BINARY ENCODER)
▶ he 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : D7 to D0
and 3 outputs : Y2, Y1 & Y0.
▶ Each input line corresponds to each octal digit and three outputs generate
corresponding binary code.
TRUTH TABLE
LOGIC CIRCUIT & BOOLEAN EXPRESSION
PRIORITY ENCODER
▶ The priority encoder is a combinational logic circuit that contains 2^n input lines and n output lines and represents the highest priority input among all the input lines.
▶ When multiple input lines are active high at the same time, then the input
that has the highest priority is considered first to generate the output.
▶ It is used to solve the issues in binary encoders, which generate wrong output
when more than one input line is active high.
▶ If more than one input line is active high(1) at the same time, then this encoder prioritizes every input level and allocates the priority level to each input.
8 to 3 Priority Encoder
▶ This kind of encoder is also named an 8-bit or Octal to Binary priority encoder.
▶ This type of encoder consists of 8 inputs and 3 outputs.
▶ When multiple inputs are active high at the same time, the input with the highest priority is considered to represent the output.
▶ For example, if D1, D2, and D3 inputs are active high or logic 1 regardless of
other input bits, then the encoded output of the priority encoder will be D3
i.e 111. Here, the D1, and D2 input bits are either irrelevant or don’t care conditions.
APPLICATIONS OF ENCODER
▶ Used in electronics industry.
▶ Automation
▶ Medical industries
▶ Robotics
▶ Digital computers, microprocessors, calculators, etc.
COMPARISON OF DECODER AND ENCODER
SR NO | ENCODER | DECODER |
1 | Basically converts the applied information signal into a coded digital bit stream. | performs reverse operation and recovers the original information signal from the coded bits. |
2 | The applied signal is the active signal input. | Accepts coded binary data as its input. |
3 | The number of inputs accepted by an encoder is 2n. | The number of input accepted by decoder is only n inputs. |
4 | The output lines for an encoder is n. | The output lines of an decoder is 2n. |
5 | Generates coded data bits as its output. | Generates an active output signal in response to the coded data bits. |
6 | The operation performed is simple. | The operation performed is complex. |
7 | Installed at the transmitting end. | Installed at the receiving side. |
8 | OR gate is the basic logic element used in it. | AND gate along with NOT gate is the basic logic element used in it. |
9 | It is used in E-mail, video encoders etc. | It is used in Microprocessors, memory chips etc. |
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MULTIPLEXERS
▶ Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
▶ One of these data inputs will be connected to the output based on the values
of selection lines.
▶ Since there are ‘n’ selection lines, there will be 2n possible combinations of
zeros and ones.
▶ So, each combination will select only one data input. Multiplexer is also
called as Mux.
2×1 MULTIPLEXER
▶ A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one
output Y.
▶ Depends on the select signal, the output is connected to either of the inputs. Since there are two input signals only two ways are possible to connect the inputs to the outputs, so one select is needed to do these operations.
▶ If the select line is low, then the output will be switched to D0 input, whereas if
select line is high, then the output will be switched to D1 input.
TRUTH TABLE
LOGIC GATE & BOOLEAN EXPRESSION
4×1 MULTIPLEXER
▶ A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select
lines as S0 and S1 and a single output line Y.
▶ The select lines S1 and S2 select one of the four input lines to connect the
output line.
▶ The particular input combination on select lines selects one of input (D0
through D3) to the output.
TRUTH TABLE
LOGIC CIRCUIT & BOOLEAN EXPRESSION
APPLICATIONS OF MULTIPLEXERS
▶ Data selection & routing
▶ Controlled sequencier
▶ Parallel to serial converter
▶ Logic function and waveform generator
DIFFERENCE BETWEEN MULTIPLEXER AND DECODER
SR NO | MULTIPLEXER | DECODER |
1 | MUX accepts several inputs and allow only one data output. | It takes n input binary code and convert it into a corresponding outputs. |
2 | Select line are used to select data inputs and allow only one of them. | Enable inputs are used to control the operation of the decoder. |
3 | It can be used in data routing and waveform generation. | Application of decoder is in Decimal to BCD encoder. |
4 | Multiplexer converts the unary code into binary code | Decoder converts binary code into unary. |
DEMULTIPLEXERS
▶ Demultiplexer is a data distributor which takes a single input and gives
several outputs.
▶ In demultiplexer we have 1 input and 2n output lines where n is the selection
line.
1×2 DEMULTIPLEXER
▶ A 1-to-2 demultiplexer consists of one input line, two output lines and one select line.
▶ The signal on the select line helps to switch the input to one of the two outputs.
▶ There are only two possible ways to connect the input to output lines, thus only one select signal is enough to do the demultiplexing operation.
▶ When the select input is low, then the input will be passed to Y0 and if the select input is high then the input will be passed to Y1.
TRUTH TABLE
LOGIC CIRCUIT & BOOLEAN EXPRESSION
1×4 DEMULTIPLEXER
▶ The 1 to 4 demultiplexer consists of one input, four outputs, and two control
lines to make selections
TRUTH TABLE
LOGIC CIRCUIT & BOOLEAN EXPRESSION
APPLICATIONS OF DEMULTIPLEXERS
▶ Communication system
▶ Arithmetic & Logic Unit (ALU)
▶ Serial to Parallel converter.
COMPARING MULTIPLEXER & DEMULTIPLEXER
SR NO | MULIPLEXER | DEMULTIPLEXER |
1 | Processes the digital information from various sources into a single source. | Receives digital information from a single source and converts it into several sources |
2 | It is known as Data Selector | It is known as Data Distributor |
3 | Multiplexer is a digital switch | Demultiplexer is a digital circuit |
4 | It follows combinational logic type | It also follows combinational logic type |
5 | It has n data input | It has single data input |
6 | It has a single data output | It has n data outputs |
7 | It works on many to one operational principle | It works on one to many operational principle |
8 | It works on many to one operational principle | It works on one to many operational principle |
9 | In time division Multiplexing, multiplexer is used at the transmitter end | In time division Multiplexing, demultiplexer is used at the receiver end |
CODE CONVERTERS: BCD TO EXCESS-3 CODE CONVERTER
K-MAPS FOR BCD TO EXCESS-3 CODE CONVERTER
LOGIC CIRCUIT
BINARY TO GRAY CODE CONVERTER
▶ The truth table for the conversion is-
K-MAP AND BOOLEAN EXPRESSION FOR BINARY TO GRAY
LOGIC CIRCUIT
GRAY TO BINARY CODE CONVERTER
▶ Truth table
K-MAP AND BOOLEAN EXPRESSION FOR GRAY TO BINARY
LOGIC CIRCUIT