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Program Concept

Hardwired systems are inflexible
General purpose hardware can do different tasks, given correct control signals
Instead of re-wiring, supply a new set of control signals

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What is a program?

A sequence of steps
For each step, an arithmetic or logical operation is done
For each operation, a different set of control signals is needed

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Function of Control Unit

For each operation a unique code is provided

e.g. ADD, MOVE

A hardware segment accepts the code and issues the control signals

We have a computer!

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Components

The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out

Input/output

Temporary storage of code and results is needed

Main memory

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Computer Components:�Top Level View

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Instruction Cycle

Two steps:

Fetch
Execute

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Fetch Cycle

Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to by PC
Increment PC

Unless told otherwise

Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs required actions

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Execute Cycle

Processor-memory

data transfer between CPU and main memory

Processor I/O

Data transfer between CPU and I/O module

Data processing

Some arithmetic or logical operation on data

Control

Alteration of sequence of operations
e.g. jump

Combination of above

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Example of Program Execution

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Instruction Cycle State Diagram

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Interrupts

Interrupt : a signal that is generated inside the computer requires the CPU to stop the current execution flow and executes other set of instructions
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
Program (Software generated interrupt due to error)

e.g. overflow, division by zero

Timer

Generated by internal processor timer
Used in pre-emptive multi-tasking

I/O (the interrupt is generated by IO device)

from I/O controller

Hardware failure

e.g. memory parity error, system power failure

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Program Flow Control

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Interrupt Cycle

Added to instruction cycle
Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction
If interrupt pending:

Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program

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Transfer of Control via Interrupts

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Instruction Cycle with Interrupts

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Program Timing�Short I/O Wait

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Program Timing�Long I/O Wait

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Instruction Cycle (with Interrupts) - State Diagram

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Multiple Interrupts

Disable interrupts

Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been processed
Interrupts handled in sequence as they occur

Define priorities

Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to previous interrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts – Nested

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Time Sequence of Multiple Interrupts

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Connecting

All the units must be connected
Different type of connection for different type of unit

Memory
Input/Output
CPU

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Computer Modules

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Memory Connection

Receives and sends data
Receives addresses (of locations)
Receives control signals

Read
Write
Timing

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Input/Output Connection(1)

Similar to memory from computer’s viewpoint
Output (similar to write)

Receive data from computer
Send data to peripheral

Input (Similar to read)

Receive data from peripheral
Send data to computer

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Input/Output Connection(2)

Receive control signals from computer
Send control signals to peripherals

e.g. spin disk

Receive addresses from computer

e.g. port number to identify peripheral

Send interrupt signals (control)

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CPU Connection

Reads instruction and data (from memory or IO)
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts

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Buses

There are a number of possible interconnection systems
Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)

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What is a Bus?

A communication pathway connecting two or more devices
Usually broadcast
Often grouped

A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels

Power lines may not be shown

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Data Bus

Carries data

Remember that there is no difference between “data” and “instruction” at this level

Width is a key determinant of performance

8, 16, 32, 64 bit

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Address bus

Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
Bus width determines maximum memory capacity of system

e.g. 8080 has 16 bit address bus giving 64k address space

🡺 Memory size = 2^{no. of address bus wires}

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Control Bus

Control and timing information

Memory read/write signal
Interrupt request
Clock signals
IO read/write signals
Interrupt Acknowledgment
Bus request
Bus grant

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Bus Interconnection Scheme

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Big and Yellow?

What do buses look like?

Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards

e.g. PCI

Sets of wires

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Physical Realization of Bus Architecture

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Single Bus Problems

Lots of devices on one bus leads to:

Propagation delays

Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcome these problems

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Traditional (ISA)�(with cache)

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High Performance Bus

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1- Bus Types (information carried on the bus)

Dedicated

Separate data & address lines

Multiplexed

Shared lines
Address valid or data valid control line
Advantage - fewer lines
Disadvantages

More complex control
Ultimate performance

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2- Bus Arbitration (who controls the bus)

More than one module controlling the bus
e.g. CPU and DMA controller
Only one module may control bus at one time
Arbitration may be centralised or distributed

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Centralised or Distributed Arbitration

Centralised

Single hardware device controlling bus access

Bus Controller
Arbiter

May be part of CPU or separate

Distributed

Each module may claim the bus
Control logic on all modules

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Timing

Co-ordination of events on bus
Synchronous

Events determined by clock signals
Control Bus includes clock line
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge
Usually a single cycle for an event

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Synchronous Timing Diagram

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Asynchronous Timing – Read Diagram

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Asynchronous Timing – Write Diagram

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Quiz1

For ODD chair number students:

1- What is the difference between data

movement and data storage ?

2- Explain “Speculative execution”

3- Explain the lines of the this module

For EVEN chair number students:

1- What does “compatibility” means?

2- Explain “branch prediction”