UK Instrumentation Bid�WP4 - DAQ & Services

K. Krizka & K. Potamianos

Liverpool Meeting�June 26-27

Target R&D towards Demonstrator (more in talk tomorrow)�Strong links with WP6 - Demonstrator

Areas of interest to WP4 - DAQ (details in backup)�Note: strong synergy with DRD7

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Electrical services w/ deep integration with mechanical structure (WP3)

• WP3 scaling up R&D from other WPs, but also new developments (SiPh)

Front-End Power : varying requirements

• Electron Collider: low power, for lightweight detector�R&D: power delivery in MAPS (WP1), power pulsing, wireless power (?)
• Hadron (& Muon) Collider: TDC consumes lots of power → copper�R&D: on-module (28 nm) DC/DC down-conversion, serial powering

Sensor bias: low power (thin) line connected to commercial power supply

Control: work on defining common interface for 4D ASICs in DRD7?

Clock: need to distribute low-jitter clocks to ASICs, can use similar technology as Readout [GHz], e.g. lpGBP (like ATLAS HGTD)

Areas of interest to WP4 - DAQ (details in backup)

Readout [GHz]: R&D based on COTS as much as possible "COTS is driven by what everybody wants. Fask links to PC and CPU exist.

• EoI to DRD7: Common interface ASIC for detector readout, timing & control
• SiPh: lots of opportunities (short- and long-term) with Silicon photonics (multiplexing, amplitude modulation)
• R&D program at CERN. Plug into it? Future Links 7.1 Presentation
• Llinks with industry: Luceda Photonics (through Europractice), IMEC
• Open issues: radiation hardness, packaging, modulator choice, multiplexing scheme, fibre
• Back-end: COTS (with software and firmware development)
• could we demonstrate usage of ethernet to communicate with FEs?

Possible projects: continuous high throughput with COTS cards, conversion from SiPh to QSFP+, rad-hard IP block for ethernet

ADDITIONAL MATERIAL

Electrical Services

• Deep integration with mechanical structure (WP3).
• Who takes care of this for the demonstrator?
• Assume this is WP3 scaling up R&D from other WP#
• ie: “old school” flex PCB with high speed lines (bare minimum)?
• ie: Daisy-chained stitched sensors from WP1?
• ie: Silicon photonics from WP4?

Front-End Power: Electron Collider

• Need to keep power usage low for a light-weight detector.
• No fancy toys in FE! (aka no TDC for fast timing).
• R&D: Power delivery in wafer size MAPS.
• This is MAPS-related R&D. Should be part of “WP1: Active Sensors”.
• Extra copper layer w/ 3D integration? Serial powering in MAPS?
• R&D: Power pulsing.
• This is ASIC-related R&D. Should be part of “WP4: ASICs”.
• References: Power pulsing with CLICpix2, CLICpix2 User’s Manual
• R&D: Wireless power. (Exploratory)
• RF power delivery
• Explore applications of power-over-Fibre delivery [O(W)]

Front-End Power: Hadron (& Muon) Collider

• Time Digital Converter takes up a lot of power!
• TIMESPOT1 numbers per channel: ADC: 10 μW, TDC: 40 μW (source).
• Power comes via copper. Need to play tricks to minimize amount.
• R&D: On-module DC/DC down-conversion.
• Artive R&D program at CERN. (ie: 28nm DC/DC converter).
• Required: development of local electronics to use CERN ASIC.
• 0.5 FTE of EE for 10 years (1 FTE at start, then ramped down).
• Material: $30k? (power supplies, test board submissions).
• Optional: characterization of CERN devices (ie: radiation hardness).
• 1 FTE of PDRA or 0.5 FTE PDRA + 0.5 PhD.
• Material: +$30k for beamtime, travel and specific setups.
• R&D: Serial powering.
• This is ASIC-related R&D. Should be part of “WP4: ASICs”.

Sensor Bias

• Low power (thin) line connected to commercial power supply
• Not necessary high voltage (add examples)
• No cutting edge R&D needed here.
• Combine effort with local electronics.

Control

• Work on defining common interface for 4D ASICs in DRD7?
• Part of WP4: ASICs, but feedback from DAQ (the other end)
• Combined effort with local electronics.

Clock Distribution

• Need to distribute low-jitter clocks to ASICs.
• ATLAS HGTD distributes 40 MHz clocks using lpGBT.
• We can use same technology as for readout.
• Combined effort with “Readout [GHz]”.

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Local Electronics

• Need someone to design the “hybrid” part of the module.
• Only applicable if we go the non-MAPs route.
• Also consider local design of sensor bias, high speed data lanes, control signals.
• Costing of a “simple design”.
• 1 FTE of EE. Can be reduced and supplemented by PDRA later in program.
• $20000 for prototype production.
• Possible R&D project: Explore alternate materials? Chiplet + 3D integration?

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Readout [GHz]: Silicon Photonics

• You can implement a lot of cool protocols using Si Photonics
• Wavelength Division Multiplexing (WDM), Spatial Division Multiplexing (SDM), Polarisation Division Multiplexing (PDM), Pulse Amplitude Modulation 4-level.
• Existing R&D program at CERN. Plug into it?
• Future Links 7.1 Presentation
• Competences at CERN, INFN, KIT and US (LBNL, FNAL, UCSB)
• Opportunity for strong links with industry (?) e.g. like IMEC (https://www.imec-int.com/en), Luceda Photonics (through Europractice)
• Interest for both short-term (HL-LHC) and longer-term (FCC, muon collider) applications
• Open issues: radiation hardness, packaging, modulator choice, multiplexing scheme, fibre
• Gain experience with COTS equipment
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Readout [GHz]: Backend Electronics: COTS All The Way

• Try to rely on COTS as much as possible.
• DRD7: "COTS is driven by what everybody wants.”
• Fast link to CPU: PCIe: (GPU, co-processors (AI)).
• Fast link to PC: Interconnects of HPCs (ie: ethernet, Infiniband, HPE slingshot)
• Extend to custom interface (ie: SiPh) using patch panels.

Can we leverage ethernet? (Internet is here to stay…)

1. Can ASICs interface be implemented using ethernet. (possible?)
2. Make a SiPh to QSFP+ patch panel (already planned?)
3. Buy QSFP+ (40 Gpbs) network cards. ($500)
4. Write software.

Readout [GHz]: Backend Electronics: COTS All The Way

• Could we demonstrate usage of ethernet to communicate with FE’s?
• Increases availability of COTS parts that we can buy (everyone networks!).

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Possible projects:

• Continuous high throughput with off the shelf cards.
• 0.5 FTE of PDRA + 1 FTE of PhD student.
• $20,000 for COTS ethernet cards (<$1000) and high-end PCs (~$2000).
• Conversion of SiPh to QSFP+
• Need 1 FTE of EE. Already in the plans?
• $10,000 for PCB. $Xk for SiPh conversion chip?
• Rad-hard IP block for ethernet
• Possible in a tracking front-end? WP4: ASICs question.

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Readout [GHz]: Backend Electronics: Backup

1. Use PCIe card with a custom mezzanine.
• Needs a firmware engineer to write firmware.
• Needs an electronics engineer to design mezzanine.
• Needs a programmer to write kernel driver + software.
2. Use an FPGA dev board with a network connection.
• Needs an electronics engineer to design mezzanine.
• Needs a programmer to implement interface of our chips.
1. Collaborate with the Caribou DAQ system to reduce extra work.
• Unclear how to scale this up. Cluster of SOC boards instead of current PC+PCIe cards?