COMPUTER ORGANIZATION AND ARCHITECTURE

Department of BCA

Loyola College of Arts and Science

Mettala

1

Unit-1

Introduction to Computer Organization and Architecture

Basic Computer Organization

• The basic computer organization has three main components:

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• CPU

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• Memory subsystem

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• I/O subsystem

Generic computer Organization

System bus

The system bus has three buses,

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• Address bus

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• Data bus

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• Control bus

Address bus

The uppermost bus is the address bus. When the CPU reads data or instructions from or writes data to memory, it must specify the address of the memory location it wishes to access

Data bus

Data is transferred via the data bus. When CPU fetches data from memory it first outputs the memory address on to its address bus. Then memory outputs the data onto the data bus. Memory then reads and stores the data at the proper locations.

Control bus

Control bus carries the control signal. Control signal is the collection of individual control signals. These signals indicate whether data is to be read into or written out of theCPU.

Instruction cycle

The instruction cycle is the procedure a microprocessor goes through to process aninstruction.

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It has three phases:

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• Fetch

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• Decode

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• Execute

Instruction cycle

• First the processor fetchesor reads the instruction from memory.
• Then it decodes the instruction determining which instruction

it has fetched.

• Finally, it performs the operations necessary to executethe instruction.
• It performs some operation internally, and supplies the address, data & control signals needed by memory & I/O devices to execute the instruction.

Control signals

•

The READ signal is a signal on the control bus which

the microprocessor asserts when it is ready to read data from memory or I/O device.

• When READ signal is asserted the memory subsystem places the instruction code be fetched on to the computer system’s data bus. The microprocessor then inputs the data from the bus and stores its internal register.
• READ signal causes the memory to read the data, the

WRITE

operation causes the memory to store the data

Timing diagrams

Memory read operation

• In fig (a) the microprocessor places the address on to the bus at the beginning of a clock cycle, a 0/1 sequence of clock. One

address READ

clock cycle later, to allow for memory to decode the and access its data, the microprocessor asserts the control signal.

• This causes the memory to place its data onto the system data bus. During this clock cycle, the microprocessor reads the data off the system bus and stores it in one of theregisters.

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• At the end of the clock cycle it removes the address from the address bus and deasserts the READ signal. Memory then removes the data from the data from the data bus completing the memory read operation

Memory write operation

• In fig(b) the processor places the address and data onto the system bus during the first clock pulse.

WRITE control signal

• The microprocessor then asserts the at

the end of the second clock cycle.

• At the end of the second clock cycle the processor completes the memory write operation by removing the address and data from the system bus and deasserting the WRITE signal.

CPUOrganization

Central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/ output (I/O) operations specified by the instructions.

CPUOrganization

• In the computer all the all the major _{components are}

connected with the help of the system bus.

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• Data bus is used to shuffle data between the various

components in acomputer system.

• When the software wants to access some particular memory location or I/O device it places the corresponding address on the address bus.
• The control bus is an eclectic collection of signals that control how the processor communicates with the rest of the system. The read and write control lines control the direction of data on the data bus.

CPU Organization

CPUOrganization

• The register section, as its name implies, includes a set of

registers

and a bus or other communication mechanism.

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• The register in a processor’s instruction set architecture are found in the section of the CPU.

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• The system address and data buses interact with this section of CPU. The register section also contains other registers that are not directly accessible by the programmer.

CPUOrganization

first bus.

• The fetch portion of the instruction cycle, the processor outputs the address of the instruction onto the address The processor has aregister ca led the ͞program counter͟.

the CPU reads

• At the end of the instruction fetch, the

instruction code from the system data bus.

usually called

• It stores this value in an internal register,

the

͞instruction register”.

CPUOrganization

• The arithmetic / logic unit (or) ALU performs most arithmetic

and logic operations such as adding and ANDing values.

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• CPUcontrols the computer, the control unit controls the CPU.The control unit receives some data values from the register unit, which it used to generate the control signals.

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• The control unit also generates the signals for the system control bus such as READ,WRITE,IO/ signals

Memory Subsystem Organization

• Memory is the group of circuits used to storedata.

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• Memory components have some number of memory locations, each word of which stores a binary value of some fixed length.

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• The number of locations and the size of each location vary from memory chip to memory chip, but they are fixed within individual chip.

Memory chips Internal organization

• Memory is usua ly organized in the form of arrays, in which each cell is capable of storing one bit information.

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• Each row of cell constitutes a memory word, and all ce ls of a row are connected to a common column ca led word line, which is driven by the address decoder on the chip

Types of Memory

• There are two types of memory chips,

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1. Read Only Memory (ROM)
2. Random Access Memory (RAM)

ROMChips

• Masked ROM(or) simply ROM

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• PROM(Programmed Read OnlyMemory)

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• EPROM(Electrica ly Programmed Read Only Memory)

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• EEPROM(Electrica ly Erasable PROM)

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• Flash Memory

ROMChips

Masked ROM

• Amasked ROM or simply ROM is programmed with dataas

chip is fabricated.

• The mask is used to create the chip and chip is designed with the required data hardwired in it.

• PROM
• Some ROM designs allow the data to be loaded by the user, thus providing programmable ROM (PROM).
• Programmability is achieved by inserting a fuse at point Pin the above fig. Before it is programmed, the ŵeŵoƌy ĐoŶtaiŶs all Ϭ’s.
• The useƌ iŶseƌt ϭ’s at the ƌeƋuiƌed loĐatioŶsďy

ďuƌŶiŶg

out the fuse at these locations using high current pulse.

• The fuses

are ďlowŶ, PROM’s

in PROM cannot restoreonce they

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ĐaŶ oŶly ďe pƌogƌaŵŵed oŶĐe.

ROMChips

• EPROM
• EPROMis the another ROM chip a lows the stored data to be erased and new data to be loaded. Such

reprogrammable ROM is usua ly ca led

an erasable an EPROM.

• Programming

in EPROM

is done by charging of capacitors. The charged and uncharged capacitors

cause each word of memory to store the correct value.

• The chip is erased by being placed under UV light, which causes the capacitor to leak their charge.

ROMChips

• EEPRO M
• A significant

disadvantage of the EPROM is the chip

is physica ly removed from the circuit for reprogramming and that entire contents are erased by the UVlight.

• Another version of EPROM is EEPROM that can be both programmed and erased electrically, such chips ca led EEPROM,do not have to remove for erasure.
• The only disadvantage of EEPROM is that different

voltages

are need for erasing, writing, reading and stored data

ROMChips

Flash Memory

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Aspecial type of EEPROMis ca led a flash memory is electrically

erase data in blocks rather than individual locations.

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It is well suited for the applications that writes blocks ofdata and can be used as a solid state hard disk. It is also used for data storage in digital computers.

Memory Subsystem Organization

• RAM

C_–h_Rip_As_M:

stands for Random access memory. This often

referred to as read/write memory. Unlike the ROM it initially contains nodata.

• The data pins are bidirectional unlike in ROM.
• AROM chip loses its data once power is removed so it is a volatile memory.
• RAM chips are differentiated based on the data they maintain.

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• Dynamic RAM (DRAM)
• Static RAM (SRAM)

Memory chips Internal organization

• Dynamic RAM

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• DRAM chips are like leaky capacitors. Initially data is stored in the DRAM chip, charging its memory ce ls to their maximum values.
• The charging slowly leaks out and would eventually go too low

to represent valid data.

• Before this a refresher circuit reads the content of the DRAM and rewrites data to its original locations.
• DRAM is used to construct the RAM in personal computers.

Memory chips Internal organization

• Static RAM

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• Static RAM are more likely the register .Once the data is written to SRAM, its contents stay valid it does not haveto be refreshed.
• Static RAM is faster than DRAM but it is also much more expensive. Cache memory in the personal computer is constructed from SRAM.

Memory chips Internal organization

• Dynamic RAM

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• DRAM chips are like leaky capacitors. Initially data is stored in the DRAM chip, charging its memory ce ls to their maximum values.
• The charging slowly leaks out and would eventually go too low

to represent valid data.

• Before this a refresher circuit reads the content of the DRAM and rewrites data to its original locations.
• DRAM is used to construct the RAM in personal computers.

Memory subsystem configuration

Multi byte organization

• There are two commonly used organizationsfor multi byte data.

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• Big endian
• Little endian

Multi byte organization

• In BIG-ENDIAN systems the most significant byte of a multi- byte data item always has the lowest address, while the least significant byte has the highest address.

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• In LITTLE-ENDIAN systems, the least significant byte of a multi-byte data item always has the lowest address, while the most significant byte has the highest address.

I/O Subsystem Organization

The I/O subsystem is treated as an independent unit in the computer The CPUinitiates I/O commandsgenerica ly

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• Read, write, scan,etc.
• This simplifies the CPU

Input Device

Input Device

• The data from the input device goes to the tri-state buffers. When the value in the address and control buses are correct, the buffers are enabled and data passes on the data bus.

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• The CPU can then read this data. If the conditions are not right the logic block does not enable the buffers and do not place on the bus.

8-bit address and

• The enable logic contains also generates

two control signals RDand I/O.

Output Device

▶ make sure that one device writes data to the bus at anytime.

🠜 Since the output devices read from the bus, rather that

▶ writes

▶ data to it, they don’tneed the buffers.

🠜 The data can be made available to all output devices but the

devices only contains the correct address will read it in

• The design of the interface circuitry for an output device such

different than for

input

as a computer monitor is somewhat the input device.

• Tri-state buffers are replaced by a register.
• The tri-state buffersare used in device interfaces to

Multi byte organization

• There are two commonly used organizationsfor multi byte data.

​

• Big endian
• Little endian

Multi byte organization

• In BIG-ENDIAN systems the most significant byte of a multi- byte data item always has the lowest address, while the least significant byte has the highest address.

​

• In LITTLE-ENDIAN systems, the least significant byte of a multi-byte data item always has the lowest address, while the most significant byte has the highest address.

Output Device

▶ make sure that one device writes data to the bus at anytime.

🠜 Since the output devices read from the bus, rather that

▶ writes

▶ data to it, they don’tneed the buffers.

🠜 The data can be made available to all output devices but the

devices only contains the correct address will read it in

• The design of the interface circuitry for an output device such

different than for

input

as a computer monitor is somewhat the input device.

• Tri-state buffers are replaced by a register.
• The tri-state buffersare used in device interfaces to

Output Device

An output device: (a) with its interface and (b) the enable logic for the registers

Output Device

• Some devices are used for both input and output. Personal computer and hard disk devices are fa ls into this category. Such a devices requires a combined interface that is essential two interfaces.
• Abidirectional I/O device with its interface and enable load logic is shown in the Figure 1.7 below.

Output Device

Figure 1.7: Abidirectional I/O device with its interface and enable/loadlogic

ASimple Computer- Levels of PL

are divided

• Computer program^mminⁱg language^gs categories.

into 3

• High level language
• Assembly level language
• Machine level language

ASimple Computer- Levels of PL

• High level languages are platform independent that is these programs can run on computers with different microprocessor and operating systems without modifications. Languages such as C++, Java and FORTRAN are high level languages.

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• Assembly languages are at much lower level of

abstraction. Each processor has its own assembly language

ASimple Computer- Levels of PL

• The lowest

level of programming language

level languages. These languages values that cause the microprocessor

contain

to perform

is machin e the

operations. When microprocessor reads and executbesinaarny instruction it’s a machine language instruction. certain

ASimple Computer- Levels of PL

Figure 1.8: Levels ofprogramming languages