BlackParrot Back End
instr
32
rs1_addr
rs2_addr
INT regfile
mem3.ird_w_v
5
5
pc
64
metadata
?
FP regfile
fp4.frd_w_v
mem3.rd_addr
mem3.rd
fp4.rd_addr
fp4.rd
PD
ISD
Decode
32
32
32
32
32
irs1
irs2
frs1
frs2
Bypass
INT1
?
instr
metadata
?
32
32
rs2
rs1
decode
Imm extract
imm
32
metadata
?
2
decode.pipe_sel
MUL1 MUL2
MEM1 MEM2 MEM3
FP1 FP2 FP3 FP4
FE-BE Rolly FIFO
rs1_addr
rs2_addr
?
?
?
?
5
5
rf_w_cmd_s (fp4)
32
nop
chk.stall
chk.rollback
8
haz_status_s (int1)
40
rf_w_cmd_s (mem3)
40
rf_w_cmd_s (mul2)
40
rf_w_cmd_s (int1)
40
8
haz_status_s (mul1)
8
haz_status_s (mul2)
8
haz_status_s (mem1)
8
haz_status_s (mem2)
8
haz_status_s (mem3)
8
haz_status_s (fp1)
8
haz_status_s (fp2)
8
haz_status_s (fp3)
8
haz_status_s (fp4)
64
pc
id.rs1_addr
id.rs2_addr
5
5
D$
EX
TLB
PTW
(irsx_addr == ird_mul1)
OR (irsx_addr == ird_mem{1,2})
OR (frsx_addr == frd_mem{1,2})
OR (frsx_addr == frd_addr{1,2,3,4})
OR (~mmu_ready)
Stall logic
NPC
64
pc
!=
64
npc
mispred
64
Exception
controller
64
64
?
exception_code
pc
MTVAL
EPC
exception_v
exception_ret_v
64
exception_v
WB
CHECKER
psn_id
psn_ex
psn_ex
psn_id
psn_id
psn_id
psn_id
psn_ex
psn_ex
psn_ex
psn_ex
psn_ex
psn_ex
Mem Arbitration
(PTW > Hit)
MMU
psn_ex
mmu_ready
Calculator
cache_miss_pc
64
cache_miss_v
32
+
4
64
64
64
int1.v
dcache_missing
BlackParrot Back End Top Level
Director
Detector
Calculator
Scheduler
Checker
npc_expected
To FE
To ME
fe_cmd (r->v)
roll_fe
flush_fe
dequeue_fe
fe_queue (v->r)
From FE
issue_pkt (r->v)
From ME
mmu_ready
calc_status
chk_psn_ex
chk_psn_isd
chk_roll
mmu_cmd (r->v)
mmu_resp (r->v)
D$
lce_cce_req (r->v)
lce_cce_data_req (r->v)
lce_cce_resp (r->v)
cce_lce_cmd (r->v)
cce_lce_data_cmd (r->v)
lce_lce_tr_resp (r->v)
lce_lce_tr_resp (r->v)
chk_dispatch
MMU
BlackParrot Checker
calc_status
NPC
en
BlackParrot Calculator
Completion Pipe
ISS
ISD
EX1
INT RF
FP RF
Issue reg
Floating Point Pipe
Memory Pipe
Multiplication Pipe
Integer Pipe
Exception Pipe
Bypass
nop
FWB
chk_poison_isd
EX2
IWB
chk_roll
chk_roll
chk_roll
cache miss
calc_status
issue_pkt (r->v)
chk_poison_ex
chk_poison_ex
chk_poison_ex
illegal_instr
chk_dispatch
issue_v
en
data
addr
w_v
rs1
rs2
data
addr
w_v
rs1
rs2
Instr
Decoder
TEMPLATE
tag_mem
512x38
mask_i
38
miss_v
0
1
miss_tag_mem_w_mask_lo
{{19{addr_i[14]}}, {19{~addr_i[14]}}}
w_i
miss_v
miss_tag_mem_w_lo
tagst_op & ready_o & v_i
data_i
miss_v
1
0
1
miss_tag_mem_data_lo
0
{2{bsg_cache_pkt_s.data[31], bsg_cache_pkt_s.data[17:0]}}
38
addr_i
v_i
miss_v
recover_lo
addr_tl_t[14]
addr_i[13:5]
miss_tag_mem_v_lo
miss_tag_mem_addr_lo
addr_i[13:5]
9
38
data_mem
4096x64
data_i
w_i
mask_i
addr_i
v_i
64
dma_data_mem_w_lo
dma_data_mem_data_lo
sbuf_data_mem_data
dma_data_mem_w_lo | (sbuf_v_lo & sbuf_yumi_li)
dma_data_mem_w_lo
sbuf_data_mem_w_mask
dma_data_mem_w_mask_lo
8
12
recover_lo
addr_tl_r[13:2]
dma_data_mem_v_lo
dma_data_mem_addr_lo
(ld_op & v_i & ready_o)
addr_i[13:2]
sbuf_addr_lo[13:2]
data_o
data_o
addr_tl_r
sigext_op_tl_r
mask_tl_r
data_tl_r
word_op_tl_r,
half_op_tl_r
byte_op_tl_r
mask_op_tl_r
ld_op_tl_r, st_op_tl_r,
tagst_op_tl_r, taglv_op_tl_r,
tagla_op_tl_r, afl_op_tl_r,
aflinv_op_tl_r, ainv_op_tl_r
bsg_cache_pkt_s.data
bsg_cache_pkt_s.mask
4
bsg_cache_pkt_s.opcode
decode
bsg_cache_pkt_s.sigext
bsg_cache_pkt_s.addr
32
addr_v_r
sigext_op_v_r
mask_v_r
data_v_r
word_op_v_r,
half_op_v_r
byte_op_v_r
mask_op_v_r
ld_op_v_r,st_op_v_r,
tagst_op_v_r, taglv_op_v_r,
tagla_op_v_r, afl_op_v_r,
aflinv_op_v_r, ainv_op_v_r
ld_data_v_r
64
18
18
tag_v_r[0][17:0]
valid_v_r[0]
tag_v_r[1][17:0]
valid_v_r[1]
32
32
32
=
=
18
addr_v_r[31:14]
32
4
(ld_op_v_r
| st_op_v_r)
(afl_op_v_r | aflinv_op_v_r | ainv_op_v_r)
tagfl_op_v_r
addr_v_r[14]
miss_handler
miss_v
write buffer
st_op_v_r,
tagfl_op_v_r,
afl_op_v_r,
aflinv_op_v_r,
ainv_op_v_r
tag_lookup
(TL)
verify
(V)
tag_mem_data_lo
tag_v_r[1:0][17:0]
valid_v_r[1:0]
36
2
dma_engine
tag_hit_v[1]
tag_hit_v[0]
2
tag_hit_v[1:0]
sbuf_empty_li
dma_send_fill_addr_lo
dma_send_evict_addr_lo
dma_get_fill_data_lo
dma_send_evict_data_lo
dma_set_lo
dma_addr_lo
dma_done_li
dma_pkt_o
dma_pkt_v_o
dma_pkt_yumi_i
dma_data_i
dma_data_v_i
dma_data_ready_o
dma_data_o
dma_data_v_o
dma_data_yumi_i
32
32
snoop_word_lo
32
dma_data_mem_v_lo
dma_data_mem_w_lo
dma_data_mem_addr_lo
dma_data_mem_w_mask_lo
dma_data_mem_v_lo
64
8
12
stat_mem
512x3
data_i
w_i
mask_i
addr_i
v_i
data_o
{st_op_v_r, st_op_v_r, tag_hit_v[1]}
miss_stat_mem_data_lo
3
miss_v
3
{tag_hit_v[1] & st_op_v_r, tag_hit_v[0] & st_op_v_r, st_op_v_r | ld_op_v_r}
miss_stat_mem_w_mask_lo
9
addr_v_r[13:5]
miss_v
(st_op_v_r | ld_op_v_r) & v_o & yumi_i
miss_stat_mem_w_lo
miss_v
miss_v
(st_op_v_r | ld_op_v_r) & v_o & yumi_i
miss_stat_mem_v_lo
miss_tag_mem_v_lo
miss_tag_mem_w_lo
miss_tag_mem_addr_lo
miss_tag_mem_data_lo
miss_tag_mem_w_mask_lo
38
38
9
miss_stat_mem_v_lo
miss_stat_mem_w_lo
miss_stat_mem_addr_lo
miss_stat_mem_w_mask_lo
miss_stat_mem_data_lo
3
3
9
3
{dirty[1], dirty[0], mru}
recover_lo
miss_done_lo
chosen_set_lo
v_o & yumi_i
ack_i
addr_v_r
32
sbuf_data_li
sbuf_mask_li
sbuf_v_li
sbuf_set_li
sbuf_data_lo
sbuf_addr_lo
sbuf_set_lo
sbuf_mask_lo
sbuf_v_lo
sbuf_yumi_li
sbuf_empty_li
32
4
ld_op_tl_r & v_tl_r & v_we
addr_tl_r
bypass_data_lo
bypass_mask_lo
32
32
4
bypass_addr_i
bypass_v_i
st_op_v_r & v_o & yumi_i
chosen_set_lo
tag_hit_v[1]
miss_v
{2{data_v_r[15:0]}}
{4{data_v_r[7:0]}}
(word_op_v_r | mask_op_v_r)
half_op_v_r
=
=
=
el1_r
el0_r
32
32
tag_hit_v_r[1]
snoop_word_lo
snoop_or_ld_data
bypass_data_masked
sigext
sigext
data_o
32
valid_v_r[addr_v_r[14]]
{tag_v_r[addr_v_r[14]], addr_v_r[13:5], 5'b0}
taglv
tagla
&
mask_v_r
miss_v
32
32
4
addr_v_r[1:0]
8
16
START
SEND_FILL_ADDR
FLUSH_INSTR
SEND_EVICT_ADDR
SEND_EVICT_DATA
RECOVER
DONE
GET_FILL_DATA
AINV
yumi_i
~miss_v
miss & (LD | ST)
miss & (AINV | AFL | AFLINV | TAGFL)
dirty & valid
~dma_finished
dma_finished & dirty & valid
~dma_finished
~dma_finished
~dma_finished
dma_finished & (dirty & valid)
dma_finished
~yumi_i
dma_finished
update tag_mem
and stat_mem
dma_finished
update tag_mem
and stat_mem
can start only if store buffer is empty.
can start only if store buffer is empty.
miss_done_lo=1
recover_lo=1
addr_v_r[1]