Dr N Umapathi, Professor/ECE�JITs – Karimnagar

Power Dissipation

7: Power

1

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Outline

• Power and Energy
• Dynamic Power
• Static Power

​

7: Power

2

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Power and Energy

• Power is drawn from a voltage source attached to the V_DD pin(s) of a chip.

​

• Instantaneous Power:

​

• Energy:

​

• Average Power:

​

7: Power

3

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Power in Circuit Elements

7: Power

4

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Charging a Capacitor

• When the gate output rises
• Energy stored in capacitor is

​

• But energy drawn from the supply is

​

​

​

• Half the energy from V_DD is dissipated in the pMOS transistor as heat, other half stored in capacitor
• When the gate output falls
• Energy in capacitor is dumped to GND
• Dissipated as heat in the nMOS transistor

7: Power

5

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Switching Waveforms

• Example: V_DD = 1.0 V, C_L = 150 fF, f = 1 GHz

7: Power

6

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Switching Power

7: Power

7

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Activity Factor

• Suppose the system clock frequency = f
• Let f_sw = αf, where α = activity factor
• If the signal is a clock, α = 1
• If the signal switches once per cycle, α = ½

​

• Dynamic power:

7: Power

8

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Short Circuit Current

• When transistors switch, both nMOS and pMOS networks may be momentarily ON at once
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are comparable for input and output
• We will generally ignore this component

7: Power

9

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Power Dissipation Sources

• P_total = P_dynamic + P_static
• Dynamic power: P_dynamic = P_switching + P_shortcircuit
• Switching load capacitances
• Short-circuit current
• Static power: P_static = (I_sub + I_gate + I_junct + I_contention)V_DD
• Subthreshold leakage
• Gate leakage
• Junction leakage
• Contention current

7: Power

10

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Dynamic Power Example

• 1 billion transistor chip
• 50M logic transistors
• Average width: 12 λ
• Activity factor = 0.1
• 950M memory transistors
• Average width: 4 λ
• Activity factor = 0.02
• 1.0 V 65 nm process
• C = 1 fF/μm (gate) + 0.8 fF/μm (diffusion)
• Estimate dynamic power consumption @ 1 GHz. Neglect wire capacitance and short-circuit current.

7: Power

11

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Solution

7: Power

12

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Dynamic Power Reduction

​

• Try to minimize:
• Activity factor
• Capacitance
• Supply voltage
• Frequency

7: Power

13

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Activity Factor Estimation

• Let P_i = Prob(node i = 1)
• P_i = 1-P_i
• α_i = P_i * P_i
• Completely random data has P = 0.5 and α = 0.25
• Data is often not completely random
• e.g. upper bits of 64-bit words representing bank account balances are usually 0
• Data propagating through ANDs and ORs has lower activity factor
• Depends on design, but typically α ≈ 0.1

​

7: Power

14

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Switching Probability

7: Power

15

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Example

• A 4-input AND is built out of two levels of gates
• Estimate the activity factor at each node if the inputs have P = 0.5

7: Power

16

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Clock Gating

• The best way to reduce the activity is to turn off the clock to registers in unused blocks
• Saves clock activity (α = 1)
• Eliminates all switching activity in the block
• Requires determining if block will be used

7: Power

17

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Capacitance

• Gate capacitance
• Fewer stages of logic
• Small gate sizes
• Wire capacitance
• Good floorplanning to keep communicating blocks close to each other
• Drive long wires with inverters or buffers rather than complex gates

​

7: Power

18

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Voltage / Frequency

• Run each block at the lowest possible voltage and frequency that meets performance requirements
• Voltage Domains
• Provide separate supplies to different blocks
• Level converters required when crossing

from low to high V_DD domains

​

​

• Dynamic Voltage Scaling
• Adjust V_DD and f according to

workload

​

7: Power

19

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Static Power

• Static power is consumed even when chip is quiescent.
• Leakage draws power from nominally OFF devices
• Ratioed circuits burn power in fight between ON transistors

7: Power

20

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Static Power Example

• Revisit power estimation for 1 billion transistor chip
• Estimate static power consumption
• Subthreshold leakage
• Normal V_t: 100 nA/μm
• High V_t: 10 nA/μm
• High Vt used in all memories and in 95% of logic gates
• Gate leakage 5 nA/μm
• Junction leakage negligible

7: Power

21

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Solution

7: Power

22

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Subthreshold Leakage

• For V_ds > 50 mV

​

​

​

• I_off = leakage at V_gs = 0, V_ds = V_DD

​

7: Power

23

Typical values in 65 nm

I_off = 100 nA/μm @ V_t = 0.3 V

I_off = 10 nA/μm @ V_t = 0.4 V

I_off = 1 nA/μm @ V_t = 0.5 V

η = 0.1

k_γ = 0.1

S = 100 mV/decade

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Stack Effect

• Series OFF transistors have less leakage
• V_x > 0, so N2 has negative V_gs

​

​

​

​

​

​

​

​

​

​

• Leakage through 2-stack reduces ~10x
• Leakage through 3-stack reduces further

7: Power

24

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Leakage Control

• Leakage and delay trade off
• Aim for low leakage in sleep and low delay in active mode
• To reduce leakage:
• Increase V_t: multiple V_t
• Use low V_t only in critical circuits
• Increase V_s: stack effect
• Input vector control in sleep
• Decrease V_b
• Reverse body bias in sleep
• Or forward body bias in active mode

7: Power

25

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Gate Leakage

• Extremely strong function of t_ox and V_gs
• Negligible for older processes
• Approaches subthreshold leakage at 65 nm and below in some processes
• An order of magnitude less for pMOS than nMOS
• Control leakage in the process using t_ox > 10.5 Å
• High-k gate dielectrics help
• Some processes provide multiple t_ox
• e.g. thicker oxide for 3.3 V I/O transistors
• Control leakage in circuits by limiting V_DD

7: Power

26

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

NAND3 Leakage Example

• 100 nm process

I_gn = 6.3 nA I_gp = 0

I_offn = 5.63 nA I_offp = 9.3 nA

7: Power

27

Data from [Lee03]

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Junction Leakage

• From reverse-biased p-n junctions
• Between diffusion and substrate or well
• Ordinary diode leakage is negligible
• Band-to-band tunneling (BTBT) can be significant
• Especially in high-V_t transistors where other leakage is small
• Worst at V_db = V_DD
• Gate-induced drain leakage (GIDL) exacerbates
• Worst for V_gd = -V_DD (or more negative)

7: Power

28

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}

Power Gating

• Turn OFF power to blocks when they are idle to save leakage
• Use virtual V_DD (V_DDV)
• Gate outputs to prevent

invalid logic levels to next block

​

• Voltage drop across sleep transistor degrades performance during normal operation
• Size the transistor wide enough to minimize impact
• Switching wide sleep transistor costs dynamic power
• Only justified when circuit sleeps long enough

​

7: Power

29

CMOS VLSI Design

CMOS VLSI Design ^{4th Ed.}