OCP NIC Community Update�July 2025

�����Sub-group Project Wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

Agenda

• 2025 OCP Global Summit
• Thermal workstream update
• NIC form factor workstream update

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2025 OCP Global Summit

• Innovation village deadline - “before July 11th”
• https://www.opencompute.org/summit/global-summit/innovation-village
• Submitted request for OCP innovation village space

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• 4 NIC related abstracts received. Close to ~30 submissions into Server: AI Co-design/NIC/HPC track

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• Event: October 13-16 2025, San Jose Convention Center
• https://www.opencompute.org/summit/global-summit/call-for-content

Thermal Workstream Update: Liquid Cooling

Exploratory work is ongoing

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• Workstream is working to understand next steps and create a clear action plan
• First step is to prove out that TSFF with cold plate is feasible both from thermal and mechanical perspective
• Satyam (Meta) has been doing early exploratory thermal studies
• Mechanical help would be appreciated to complete feasibility study

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• Looking to get more expertise and participation both from system vendors and NIC vendors

Thermal Workstream Update: Test Fixtures

DSFF Thermal Test Fixture (TTF)

• Dell shared the initial draft of mechanical files uploaded to the OCP NIC WIP drive
• Thank you!!!
• Workstream will use these files to start spec work
• Create detailed thermal model
• Generate appropriate design guidance and plots
• Question raised about Gen 6 complaint SFF TTF
• Will one be made?
• Will DSFF TTF the standard going forward?
• If so, what is the BKM for usage?
• 1 DUT, 1 dummy? 2 DUTs?

Form-factor workstream: Categories of NICs

1. Low Speed LOM, 1G, 10G served well by RJ45
2. High Speed NIC, mostly use in Front-End/CPU. Could use in Back-end/GPU if space allow.
3. Smart NIC with offloading capabilities
4. Ultra High Speed NIC, Back-end/GPU focused, High-density

Form-factor workstream:

Why Ultra High Speed NIC not served optimally by existing form factors?

• CEM & SFF limits to 16 PCIe lanes
• APEC, PMM, DSFF PCIe IO by SFF-TA-1002 goldfinger, standard IO density
• APEC or PMM could be a good starting point

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• If we engage in a new form factor development given newer process node doesn’t natively support 3.3v, as new form factor, we should investigate 1.8v/1.2v IO together

Form-factor workstream: Comparison between form factors

Form-factor workstream: What are we try to solve for?

• Higher density & higher bandwidth NIC solution than PMM offering today
• More PCIe lanes in smaller dimension
• X dimension (Faceplate)
• Y dimension (System Depth)
• Z dimension (Faceplate)
• Support 64 PCIe lanes
• 32 PCIe lanes at half size ideally works too but would be even more challenging
• Board thickness
• Observed 1.6mm NIC PCB thickness is limiting layer counts in some use-case

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• Next steps:
• Broadcom, Dell & Nvidia co-work to identify if there are more gaps compared to PMM

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Thank You

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We’re Accepted in the Contribution Database!

OCP NIC 1.6.0 has been formally accepted into the contribution database:

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https://www.opencompute.org/contributions → Query for OCP NIC 3.0 Specification 1.6

DSFF Thermal Test Fixture Overview

• New DSFF TTF will support SFF / TSFF / DSFF form factors at PCIe^® speeds up to Gen 7
• Metal housing with a PCB designed to extend PCIe lanes from a DC-MHS compatible server to a mounted OCP 3.0 DUT card
• Intended to attach to a wind tunnel or flow bench
• Pre-defined sensor locations for test repeatability
• Onboard MCU shall operate same as prior thermal test fixtures and codebase will be uploaded to the Github repository
• Update: protos arrived. Dell & Intel are bringing up units
• Successfully got the TTF + OCP NIC to connect to an HPM via MXIO cable and pass traffic!
• Issues found: VRegs settings updated, SMBus mis-wired, MCU power fix, clock buffers not powered, 2nd clock mis-wired
• Next steps
• Thermal testing, finish developing MCU code to support DSFF & SFF DUTs… new PCB board spin

DSFF Thermal Test Fixture

DSFF TTF Airflow Operation

Please note: PCIE^® design mark is a registered

trademark and/or service mark of PCI-SIG.

DSFF SI Update - no progress

• Dell contributing DSFF CBB SI fixture, Gen 6 by default
• Schematic & Board files here: Link
• Testing current prototype
• Intel uncovered secondary clock tree missing 100 MHz input clock impacting the secondary connector’s clocks; new board revision required; Intel shows passing results otherwise (report to be uploaded to our google drive)
• Broadcom reporting SSC circuit not �working; currently in debug.

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• For DSFF CLB use two of CLB SFFs, which current Gen 5 fixture able to support Gen 6 SI testing

We should start the�Gen 7 NIC specs

What are the public form factors for NICs today?

• These are public form factors from PCI-SIG, OCP & SNIA organizations
• There are also non-public form factors that in-use by hyperscalers & major vendors

PCIe CEM

APEC

SFF

DSFF

PMM

Runway of OCP NIC 3.0 SFF

QSFP

QSFP

OSFP

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QSFP-DD

ASIC

ASIC

4x224G

4x224G

8x224G

PCIe Gen6 x16 => 800G

PCIe Gen7 x16 => 1.6T

PCIe Gen6 x16 => 800G

PCIe Gen7 x16 => 1.6T

SerDes Limit

PCIe Limit

Thermal Limit

Comparison between form factors

Some ASIC near Cage form factor ideas

Start from DSFF depth

Start from PMM depth

Start from CEM depth

Some ASIC near Cage form factor ideas

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Start from DSFF depth

Start from PMM

depth

Start from CEM depth

Further studies

64 PCIe lanes

32 Side bands

450W 12v power delivery

64 PCIe lanes

32 Side bands

600W 12v power delivery

64 PCIe lanes

32 Side bands

600W 12v power delivery

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Short PMM/

CEM Depth

Long PMM Depth

Long PMM Depth