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ePixUHR Requirements and timeline

TID-ID Edge Computing Systems

Specification
Mode	35 kHz	100 kHz
Pixel Pitch [um]	100
Frame rate [kHz]	35	100
Matrix size	192 x 168
Read Noise [e^- rms]	150
Well depth [8keV photons]	10⁴ ^{(can only test with charge injection up to 5%)}
Power consumption [W/cm²]	1.2
Data rate [Gb/s]	16	44
CMOS tech node	TSMC 130 nm

ePixUHR-v1:

Submitted October 2022
Goal: demonstrate architecture at full-scale
Pixel was not optimized for 35kHz operation
ADC performance meeting specs

ePixUHR-v2:

Submitted December 2023
Goal:

Standardize ASIC-FPGA links: �LVDS 🡪 CML + Pgp4Lite
Design pixel for 35kHz operation, possibly 100kHz

ePixUHR-v3:

Submitted August 2024
Goal:

Fix the issues found in v2

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ASIC Architecture

TID-ID Edge Computing Systems

Pixel matrix: 192 (H) x 168 (V) - Clusters

Readout

x8 CML outputs @ 6.25 Gb/s

Slow control & analog bias

ePixUHR ASIC

Readout

Si Sensor �100 µm pitch

Serializers & clock spine

Pixel matrix

Balcony

19.3 mm

18.2 mm

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GTReadout Platform

TID-ID Edge Computing Systems

Analog Board

Monitoring ADCs

High Speed for oscilloscope-like power monitoring
Environmental (Temperature, Humidity and voltages)

DACs

ASIC Calibration and Charge injection
Sensor Guard Ring

Carrier Board

It will host a tile of 2x2 ASIC/Sensor
Large cutout for cooling
500-pin Samtec SEAM8 Connector

Digital Board

Kintex Ultrascale+ FPGA (KU15P-A1760)
300Gbps Amphenol Leap OBT optical transceiver
Clean fast clocks generation

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ePixUHR-v3

TID-ID Edge Computing Systems

ASIC received on 17^th December 2024

We received 2 carrier boards, each one has 2 ASIC bonded on the left side,

on the positions of ASIC 1 and ASIC 4

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Fixed Issue #1: Leakage in pixel memory

TID-ID Edge Computing Systems

In v2 the leakage current of the pixels analog memories was too high. The sampled voltages would decay faster than the readout speed, causing a gradient that was dependent on the readout order

ePixUHR-v2

ePixUHR-v3

The leakage of the analog memories was fixed.�The clusters do not show the gradient dependent on the pixel position anymore.

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Fixed Issue #2: ADC non-linearity due to supply/ground bounce

TID-ID Edge Computing Systems

ePixUHR-v2

ePixUHR-v3

UHR-v2 used a new architecture for ADC reference buffers to reduce power and noise at the cost of lower PSRR. Observed noise coupling due to supply/ground bounce, affecting A/D linearity.

For UHR-v3 we reverted back to the reference buffers used in v1

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CSA Noise

TID-ID Edge Computing Systems

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Registers Tuning

TID-ID Edge Computing Systems

We have 7 main analog registers that we need to tune, which will affect noise, linearity and power consumption of the ASIC.

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Weighting Function

TID-ID Edge Computing Systems

We are tuning the non-linear low pass filter after the CSA. This trades noise for filter bandwidth

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Power consumption

TID-ID Edge Computing Systems

ePixUHR-v2 sim

ePixUHR-v3 simulation

2.44 A (default settings)�1.93 A (current settings)

0.416 A

ePixUHR-v3 measured

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Charge Injection Circuitry: Recap

TID-ID Edge Computing Systems

ADC

Pixel

External DAC

16-bit AD5541

FPGA

ePixUHR

Pixel Inj Register

Inj

C_inj

Sensor

DAC

ePixUHR has a single injection line that is fed to all pixels at the same time

With the DAC we’re able to both set a single value and create a ramp which is triggered by the SRO signal, to have an easier testing.

Using the pixel gain registers we are able to decide which pixel are enabling injection, but for simplicity the following tests have been done with 100% occupancy.

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1) Fixed High Gain Map

TID-ID Edge Computing Systems

Here all pixels were injected at the same time(100% Occupancy).�Given the ramps, we are able to fit each of the ramps and calculate the gain

Measured median Noise = 1.29 ADUs
Cinj gain = 5.2 keV/mV
Average gain = 3.38 ADU/keV
Noise in eV = Noise/Gain = 378 eV
Noise in el- = 105 el-

This is without sensor! Probably worse when connected

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2) Fixed Medium Gain Map

TID-ID Edge Computing Systems

Measured median Noise = 1.01ADUs
Cinj gain = 5.2 keV/mV
Average gain = 1.30 ADU/keV
Noise in eV = Noise/Gain = 777 eV
Noise in el- = 215el-

This is without sensor! Probably worse when connected

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3) Fixed Low Gain 1 (40 MeV) Map

TID-ID Edge Computing Systems

Measured median Noise = 1.0 ADUs
Cinj gain = 5.2 keV/mV
Average gain = 0.046 ADU/keV
Noise in eV = Noise/Gain = 21.7 keV
Noise in el- = 6038 el-

This is without sensor! Probably worse when connected

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4) Fixed Low Gain 2 (80 MeV) Map

TID-ID Edge Computing Systems

Measured median Noise = 0.92 ADUs
Cinj gain = 5.2 keV/mV
Average gain = 0.0231 ADU/keV
Noise in eV = Noise/Gain = 39.8 keV
Noise in el- = 11063 el-

This is without sensor! Probably worse when connected

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ePixUHR-v3 measured gain and noise (without sensor)

TID-ID Edge Computing Systems

Gain mode	Noise [e-]	Gain [keV/ADU]	Range	Notes
High-gain	105	3.38	> 350 keV
Medium-gain	215	1.30	> 1 MeV	Gain ratio HG/MG = 2.6
Low-gain 1 (LG1)	∼ 6000	0.046	< 40 MeV	Gain ratio HG/LG1 = 74
Low-gain 2 (LG2)	∼ 11000	0.023	< 80 MeV	Gain ratio HG/LG2 = 147

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Automatic gain switching

TID-ID Edge Computing Systems

I just started with the study of the ramps in auto-gain, but we don’t see glitches at the switching points and the linearity plots are promising for now.

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BACKUP

TID-ID Edge Computing Systems

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Pixel matrix architecture

Operates at 35 kHz – 1 MHz
Si sensor: 100x100 µm²
ASIC: 50x100 µm²

Pixel

Cluster

72 pixels 🡪 1 ADC @ 8 MSPS
Digital logic for pixel configuration and readout

ADC

Digital

logic

1200 µm

600 µm

50 µm

100 µm

Tile to create pixel matrix: 192 x 168

14 clusters in vertical direction
16 clusters in horizontal

ASIC

72 pixels 🡪 1 ADC @ 8 MSPS
Digital logic for pixel configuration and readout