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Definitions

Propagation delay time, tpd = maximum time from the input crossing 50% to the output crossing 50%
Contamination delay time, tcd = minimum time from the input crossing 50% to the output crossing 50%
Rise time, tr = time for a waveform to rise from 20% to 80% of its steady-state value
Fall time, tf = time for a waveform to fall from 80% to 20% of its steady-state value
Edge rate, trf = (tr + tf)/2

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Fig: Propagation Delay and Rise/fall times

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Timing Optimization

There will be several critical paths that limit the system’s operating speed and require attention to timing details.
The critical paths can be affected at four main levels:
The architectural/ microarchitectural level
The logic level
The circuit level
The layout level

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Transient Response

The most fundamental way to compute delay is to develop a physical model of the circuit of interest, write a differential equation describing the output voltage as a function of input voltage and time, and solve the equation.
The solution of the differential equation is called the transient response, and the delay is the time when the output reaches VDD /2.

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The differential equation is based on charging or discharging of the capacitances in the circuit.
The circuit takes time to switch because the capacitance cannot change its voltage instantaneously.
If capacitance C is charged with a current I, the voltage on the capacitor varies as

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RC Delay Model

RC delay models approximate the nonlinear transistor I-V and C-V characteristics with an average resistance and capacitance over the switching range of the gate.
This approximation works remarkably well for delay estimation despite its obvious limitations in predicting detailed analog behavior

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Effective Resistance

The RC delay model treats a transistor as a switch in series with a resistor.
The effective resistance is the ratio of Vds to Ids averaged across the switching interval of interest.
A unit nMOS transistor is defined to have effective resistance R.

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Gate and Diffusion Capacitance

Each transistor also has gate and diffusion capacitance.
We define C to be the gate capacitance of a unit transistor of either flavor.
A transistor of k times unit width has capacitance kC.
Diffusion capacitance depends on the size of the source/drain region.

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Equivalent RC Circuits

Fig : Equivalent Circuit for an inverter

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Elmore Delay

The Elmore delay model [Elmore48] estimates the delay from a source switching to one of the leaf nodes changing as the sum over each node i of the capacitance Ci on the node, multiplied by the effective resistance Ris on the shared path from the source to the node and the leaf.

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Layout Dependence of Capacitance

In a good layout, diffusion nodes are shared wherever possible to reduce the diffusion capacitance

Fig: 3-input NAND annotated with diffusion capacitances extracted from the layout

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Linear Delay Model

The RC delay model showed that delay is a linear function of the fanout of a gate.
Based on this observation, designers further simplify delay analysis by characterizing a gate by the slope and y-intercept of this function.
In general, the normalized delay of a gate can be expressed in units of Y as

d = f + p

p is the parasitic delay inherent to the gate when no load is attached.

f is the effort delay or stage effort that depends on the complexity and fanout of the gate

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f = gh

The complexity is represented by the logical effort, g.
An inverter is defined to have a logical effort of 1.
A gate driving h identical copies of itself is said to have a fanout or electrical effort of h.
If the load does not contain identical copies of the gate, the electrical effort can be computed as

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Logical Efforts
Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current.
Parasitic Delay
The parasitic delay of a gate is the delay of the gate when it drives zero load.
It can be estimated with RC delay models.

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Logical Efforts of Paths

Designers often need to choose the fastest circuit topology and gate sizes for a particular logic function and to estimate the delay of the design.

The techniques of Logical Effort is used to understand the delay of many types of circuits.

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Delay in Multistage Logic Network

the logical and electrical efforts of each stage in a multistage path as a function of the sizes of each stage.

Fig: Multistage Logic Network

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The path logical effort G can be expressed as the products of the logical efforts of each stage along the path

The path electrical effort H can be given as the ratio of the output capacitance the path must drive divided by the input capacitance presented by the path.

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The path effort F is the product of the stage efforts of each stage.

Branching effort b is the ratio of the total capacitance seen by a stage to the capacitance on the path

The path branching effort B is the product of the branching efforts between stages.

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Fig: Circuit with two way branch

Circuit Design Processes

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Choosing the best number of Stages

Fig: Comparison of different number of stages of buffers

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Combinational Circuit Design

Introduction
Digital logic is divided into combinational and sequential circuits.
Combinational circuits are those whose outputs depend only on the present inputs.
while sequential circuits have memory.

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Circuit Families

Static CMOS circuits with complementary nMOS pulldown and pMOS pullup networks are used for the vast majority of logic gates in integrated circuits.

They have good noise margins, and are fast, low power, insensitive to device variations, easy to design, widely supported by CAD tools, and readily available in standard cell libraries

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Static CMOS

Designers accustomed to AND and OR functions must learn to think in terms of NAND and NOR to take advantage of static CMOS. In manual circuit design, this is often done through bubble pushing
Bubble Pushing: CMOS stages are inherently inverting, so AND and OR functions must be built from NAND and NOR gates.
DeMorgan’s law helps with this conversion:

Fig: Bubble pushing with Demorgan’s Law

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Compound Gates: static CMOS also efficiently handles compound gates computing various inverting combinations of AND/OR functions in a single stage

Fig: Logic using AOI22 gate

Input ordering delay effect
Asymmetric Gates
Skewed gates

Fig: Catalog of Skewed gates

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Ratioed Circuits

Ratioed circuits depend on the proper size or resistance of devices for correct operation.
Psuedo nMOS: pseudo-nMOS inverter is shown below

Fig: pseudo-nMOS inverter

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Cascode Voltage Switch Logic: Cascode Voltage Switch Logic seeks the benefits of ratioed circuits without the static power consumption.
It uses both true and complementary input signals and computes both true and complementary outputs using a pair of nMOS pulldown networks

Fig: CVSL Logic

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Dynamic Circuits: The drawbacks of ratioed circuits include slow rising transitions, contention on the falling transitions, static power dissipation, and a nonzero VOL. Dynamic circuits circumvent these drawbacks by using a clocked pullup transistor rather than a pMOS that is always ON.

Fig: Comparison of static pMOS, Psuedo nMOS and Dynamic Inverter

Circuit Design Processes

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Domino Logic: The monotonicity problem can be solved by placing a static CMOS inverter between dynamic gates.

Fig: Domino Logic

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Pass transistor Circuits: In pass-transistor circuits, inputs are also applied to the source/drain diffusion terminals.
These circuits build switches using either nMOS pass transistors or parallel pairs of nMOS and pMOS transistors called Transmission Gates (TG).

Fig: TG

There are wide variety of alternative pass-transistor families listed below:
CMOS with Transmission Gates:
Complementary Pass Transistor Logic
Lean Integration with Pass Transistors (LEAP)

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Text Books

1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

Note : Images and figures have been taken from prescribed textbooks.

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Reference Books

1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition, Oxford University Press, International Version, 2009.
2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition – 1994).
3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.