�Call for participation in new White Paper

D2D Chiplet Interface Testing

OCP Sponsored Tutorial

Speakers = Madhumita Sanyal (Synopsys Inc), Pavan K (Tessolve)

Contributors = Mike Bartley (Tessolve), James Wong (Palo Alto Electron), Boon Chong Ang (Intel), Prasad Mantri (Tessolve)

Agenda

• Problem statement
• Current status of chiplet test
• Chiplet based SiPs - 2.5D → 3D
• Prudence during chip testing
• Accelerating test
• System Level and Functional Tests
• Example UCIe : KGD Testing and Assembly Yield Recovery
• Test Cost
• Comparison of Test Costs
• Standards
• Summary and next steps

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Objectives

• Call for participation in a White Paper
• “D2D Chiplet Interface Testing”
• To be presented at the Chiplet Summit in October 2024
• Schedule
• Mid-Feb’24 : list of volunteer contributors
• End-Feb’24: white paper skeleton (based on this ppt) and sections assigned
• End-April’24: first draft
• End June’24: second draft
• End-August’24: final version
• October’24: White-paper to be presented at Global Chiplet Summit

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Problem statement

In multi-die packages, one bad die can result in the failure of the whole package. Heterogeneous integration within the package involve complexities that drive the need for effective screening for high yields and long-term reliability

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Current Status of Chiplet Test

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• Existing example solution for chiplet test

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• IEEE P1838+1149.1

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• Scan traffic over Native PCIe/USB protocol

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• Mux-ed with PCIe/USB/other HSIO PHY

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• Direct IOs through active interposer with isolation mode

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• SiP will get more complex with Dense TSV based chiplets (near Mem. 3D)
• Greater heterogenous packaging with Si and Glass interposers requiring more complex packaging, assembly and Test.

Chiplet based SiPs - 2.5D → 3D

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• For a D2D construction, KGD is implicit. (FT Yield/Cost)
• All Die need Die-id that can be accessed via control die. (Planning/Logistics/RMA)
• Besides Structural test, Maximum functional test need to be planned for higher SIP yield. (Test/Yield)
• For 3D construction, stack die testing needs to be included in the probe flow and needs to be done in fab.(Cost)

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• D2D connect - interposer, TSV or substrate, thermal- signal degradation, Design to consider constant ckt tuning
• Test Assembled package in mission mode, need contactless debug capability accessing every die.(Technical)

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Controller (Base) die –

• Accommodate its ID, SIP ID and all companion id’s including telemetry.
• Handle both mission mode and test mode security, power on sequence of companion die’s.
• Capability to monitor and modulate, power, temp. and other critical features of the companion dies.(Technical)

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Prudence during chiplet testing�(Test, Qual, Char)

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• DFF is essential. Test data from previous to next insertion. Robust IT network and backup becomes essential
• Data flow and security risks to be addressed. OSAT adds additional risk.
• As different die in the package run at different temperature, arriving at the correct test temp is a challenge.(Technical)
• Provision to run all structural test similar to individual dies in the final package part. (Debug & FA)

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• Advanced compression techniques: High compression CODECs, SSN to minimize data volume
• BIST & BIRA on memories with incremental repair (Accounting for Temp, power & noise variations across die on SIP).
• Need DVFS like feature in test mode to monitor Power & Thermal, mainly during reliability screening
• HSIO & D2D interfaces will require careful loopback architecture - internal loopback, pad loopback, far-end loopback, full eye-diagram testing, monitoring and tuning when assembled.
• Ability to have incremental repair to do multiple repairs, IFR (infield repair) and alter configurations.

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Prudence during chiplet testing�(Test, Qual, Char)

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• Delivering data (Patterns) across multiple dies using existing HSIO or D2D Interface can be a game changer..
• One solution to deliver high volume pattern into each of the chiplets is to use the IEEE 1149.10 HSTAP IP standard, when connected to SSN sets high speed patch across chipets with no additional test pins.
• SSN network is an efficient test pattern streaming network into the design and getting the test results back out for comparison on the tester.

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• Its asynchronous interface allows ability to deliver balance data volume across various IPs on the chiplet with diverse data requirements and aiding concurrent testing , resulting in significant test time reduction

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• SSN is becoming a universal test access mechanism for most advanced chips.

Accelerating test - Test access and Test time

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• In 3D structure, Interposer and dies are stacked one above another.
• Dies interact among each other with TSVs (Through Silicon Vias), made of a pillar-like structure with Copper, Tungsten or Poly through silicon that provides electrical interconnects through a silicon die or through-wafer.
• A Chip containing TSVs is subjected to experience a variety of reliability effects on BEOL and FEOL structures.

•  The coefficients of thermal expansion (CTEs) of the silicon die and package materials, such as plastic molding compounds or organic substrates, differ significantly.
• This CTE mismatch induces thermo-mechanical stresses at the interfaces during thermal excursions, The influence of the package-induced stress on the chip is called chip-package interaction (CPI), and it plays a key role in overall product reliability.
• To meet electrical performance requirements of high-performance CMOS devices, engineers use low-k (dielectric constant), and more recently ultra-low-k (ULK) or extreme low-k (ELK), dielectric materials along with copper (Cu) interconnects. However, the mechanical strength of the material deteriorates with lower k, raising more concerns on thermo mechanical reliability.

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JEP158 – 3D Chip Stack with Through- Silicon Vias ( TSVS) : Identifying , Evaluating and Understanding Reliability Interactions

• This standard covers only the interaction between the 3D TSV component , the semiconductor package and Device
• 3D chip stacks are affected by the same stress as single chips but the tier and TSV add more structures and complexity to the system
• Traditional CPI structures can be used to evaluate the inter-connections between strata in the 3D stack and between the chip stack and the package.
• New structures are used here to evaluate the TSV intra-connection.

Reliability Challenges due to TSV ,CTE , CPI

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KGD Testing and Assembly Yield Recovery

• High test coverage of naked die with
• Internal and External loopback modes
• Random and Programmable test pattern generation and matching
• IDDQ and Burn-in test modes
• BIST of critical blocks
• Scan chains, etc
• Integration in the on-die and multi-die hierarchical test solution for
• Supports naked die and assembled die testing
• Access to all dies via bottom/main die JTAG
• Allows optimal sequencing of tests to reduce test time
• Simplifies test pattern creation by re-use from individual IP level
• Test and Repair of individual D2D traces at startup
• Recovers yield loss from package assembly

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Built in Testability & Repair Functionality Minimizes Yield Loss

3D SHS Hierarchical Test Solution

Test & Repair Solution

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Chiplet Testability Architecture for KGD

UCIe PHY built in DFT for high test coverage

• Naked die and after assembly

Test and Repair of individual D2D traces

• Recovery of yield loss from package assembly
• Repair signature storage

Multi-die hierarchical test solution

• For faster production test in all phases
• Fast test access through UCIe D2D interface

Built in Testability & Repair Functionality Minimizes Yield Loss

3D SHS Hierarchical Test Solution

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UCIe Test and Repair Capabilities

• UCIe Advanced
• Failing pins are identified at in Test and Repair phase during PHY initialization
• All pins can be repaired, PHY includes:
• 8 repair pins for TX & for RX
• 4 repair pins for mainband data, 1 for clks and track
• 1 repair pin for valid, 1 for sideband data, 1 for sideband clk
• After Repair, performance is maintained

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• UCIe Standard
• Failing Link is identified during mission mode with parity checks
• No repair pins available
• PHY goes to degraded mode where only half the pins remain active
• In degraded mode, performance is half of normal mode
• Failures on clock, valid, SB are fatal

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Higher Yield Standard Package Enables Simpler Repair

Degraded Mode

UCIe-A

UCIe-S

Stopped pins

Active pins

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D2D Interface Failure Prediction & Repair

Avoids System Outage w/

• Per-lane health monitoring
• Lane Testing (algorithmic)
• Lane Repair (cumulative)

Synopsys Architecture w/

• Built-in SIM in UCIe-A PHY
• Mission mode eye-diagram monitoring & repair
• Power-on Self-Test & Repair
• Embedded and cloud analytics for real time control & fleet statistic

With Synopsys UCIe and SLM Solution

Signal Integrity Monitor

Operation Concept

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Test Cost

• Target test cost is not to exceed 20% of the die cost as a rule of thumb.
• Factors that influence testing cost:
• Required test time is equal to the product of # of scan patterns, scan chain length, and scan shift frequency. This governs manufacturing testing cost
• Modern DFT techniques like test compression and increasing shift frequency can reduce scan chain lengths and increase shift frequency to reduce test time and cost
• Wafer probe testing requires wafer-level equipment to test known good die (KGD) after packaging impacts gross margin
• Module-level testing requires enabling retargeted tests of each chiplet from the top-level controller in separate test sessions for the chiplets and inter-die connections
• Parallel chiplet testing can reduce final test cost when possible through architectural means and staying within power constraints
• Reference: OCP, Business Analysis of Chiplet-Based Systems and Technology, scheduled for release around the Chiplet Summit 2024

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Comparison of Test Costs

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Standards

• OCP whitepaper: Proposed Standardization of Chiplet Models for Heterogeneous Integration/Chiplet Design Kits (CDK) - Recommends the standards for chiplet testing
• https://www.opencompute.org/documents/ocp-odsa-cdx-proposed-standardization-of-chiplet-models-for-heterogeneous-integration-2-pdf
• IEEE 1149.1 (JTAG) - Standard for Test Access Port and Boundary-Scan Architecture.
• IEEE 1687 - Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device with interfaces suitable to be hosted under the IEEE 1149.1 Test Access Port (TAP).
• IEEE 1838 - Standard for test access architecture for 3D IC.
• CDXML/JEP30 - OCP/JEDEC joint effort of XML Schema for chiplet data exchange
• https://github.com/opencomputeproject/ODSA-CDXML
• OCP whitepaper: Guide to Integration Workflows for Heterogeneous Chiplet Systems - Testing workflows for multi-die System-in-Package- To be released during Chiplet Summit 2024.
• IEEE 3405 - Standard for Chiplet Interconnect Test and Repair.

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Summary and next steps

• We are proposing a new white paper on “D2D Chiplet Interface Testing”

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• We plan to present this at the chiplet summit in October

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• Please contact Mike Bartley to contribute

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• Mike.bartley@tessolve.com

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