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Open PMIC

Test Results

Weston Braun

Aparna Tumkur

Github: https://github.com/westonb/open-pmic

https://github.com/westonb/Open-PMIC-tapeout

https://github.com/westonb/open-pmic-pcb

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System Block Diagram

Power Circuitry

Control

Circuitry

Support /

Debug

Current Mode Buck Converter, 3.3V in, 1.8V out, 300mA output current

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Test PCB

  • Flash + programming header for management core
  • Current DAC for bias inputs
  • Monitored power rails
  • DC Load
  • Debug inputs + test points

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Test Results

  • System Level Tests
    • Efficiency
    • Transient Response
  • Power Stage Characterization
  • Current Sense Characterization
  • Error Amplifier Characterization

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Test Results - Efficiency

3.3V Input, 1.8V Output

450 kHz switching frequency

Simulated

Measured

Efficiency difference largely attributed to resistive losses in connections to user project area

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2.4 mA of bias current when idle

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Test Results - Transient Response

  • Open circuit to 6 ohm load step
  • 3% over/undershoot
  • No significant non-linearities at min/max of commanded current range
  • Tested from input voltage of 2.5 V to 4.0V
  • 1.79V DC output voltage

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C2: Switching Node

C3: Output Voltage (AC Coupled)

C4: Inductor Current

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Test Results - Power Stage

  • Switches in less than 1.5 ns
  • 0.5nC combined gate + output charge
  • 1.7mW/MHz no load switching loss

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Simulated

Measured

NMOS Resistance

175 mΩ

220 mΩ

PMOS Resistance

325 mΩ

390 mΩ

I/O Interconnect Resistance

0 Ω

315 mΩ

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Test Results - Current Sense

  • On chip current sense monitored via current mirror output and TIA on test PCB
  • Only measures PMOS current

C1: Switching Node

C3: Inductor Current

C4: Current Sense Output

Settling Time

< 60 ns

Bandwidth

> 10 MHz

Gain Error

5%

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Test Results - Error Amplifier

Test circuit allows for characterizing amplifier Gm and gain

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2 measurements with different Cload to extract Gm

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Tested with 1V common mode voltage

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Simulation

Test

Gm

1.0 mS

0.88 mS

Gain

49.3 dB

49.2 dB

Offset Voltage

0.7 mV

2.4 mV

Parasitic Pole Frequency

230 MHz

> 70 MHz

PMOS input output transconductance amplifier

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Contributions / Summary

Layout of hybrid waffle PMOS/NMOS power stage is being used by at least one other team designing on SKY130

All basic building blocks for power converters on SKY130 silicon proven!

IC meets initial design goal (>85% peak efficiency)

Working on paper on IC design

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Questions

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Extra

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Target Specifications

Nominal Vin

3.3V

Vout

1.8V ±5%

Maximum Output Current

300mA

Switching Frequency

>300kHz

Efficiency

>85%

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Bonus Die Decap Photos

vs

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Test Board Photo

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Current Sense - Schematic

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Current Sense - Small Signal Validation

Open Loop Response: Phase margin of 45 degrees

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Closed Loop Response: -3dB point at 18MHz

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Open Loop Frequency Response

Closed Loop Frequency Response