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Please read this disclaimer before proceeding:

�This document is confidential and intended solely for the educational purpose of RMK Group of Educational Institutions. If you have received this document through email in error, please notify the system manager. This document contains proprietary information and is intended only to the respective group / learning community as intended. If you are not the addressee you should not disseminate, distribute or copy through e-mail. Please notify the sender immediately by e-mail if you have received this document by mistake and delete this document from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited.

R.M.K. ENGINEERING COLLEGE����24EC102 DIGITAL PRINCIPLES AND

SYSTEM DESIGN �(Lab Integrated)

Department: Electronics and Communication Engineering

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Batch/Year: 2024-2028 / I

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Created by:

Dr. Meena Kumari

Mr. Joel T

Mrs. S. Karkuzhali

Mr. Shyam M

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Date: 1^st November, 2024�

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Table of Contents

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Table of Contents

1. Course Objectives

• To acquire the knowledge in Digital fundamentals and its simplification methods.
• To familiarize the design of various combinational digital circuits using logic gates.
• To realize various sequential circuits using flip flops.
• To interpret various clocked sequential circuits.
• To elucidate various semiconductor memories and related technology.
• To build various logic functions using Programmable Logic Devices.

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• 20PH102 Physics For Electronics Engineering

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2. Pre-requisites

24EC102 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C

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UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9

Review of number systems-representation-conversions, Review of Boolean algebra- theorems, sum of product and product of sum simplification, canonical forms, min term and max term, Simplification of Boolean expressions-Karnaugh map, Implementation of Boolean expressions using logic gates and universal gates.

List of Exercise/Experiments:

1. Implementation of Boolean expression using logic gates.

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UNIT II COMBINATIONAL LOGIC CIRCUITS 9

Design of combinational circuits - Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, Magnitude Comparator, Decoder, Encoder, Priority Encoder, Mux/De-mux, Parity Generator/Checker

List of Exercise/Experiments:

2. Design of adders

3. Design of subtractors.

4. Design of binary adder using IC7483

5. Design of Multiplexers & Demultiplexers.

6. Design of Encoders and Decoders.

7. Implementation of a boolean function using a multiplexer

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UNIT III SEQUENTIAL CIRCUITS 9

Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Asynchronous and Synchronous Counters Design - Shift registers, Universal Shift Register

List of Exercise/Experiments:

8. Design and implementation of 3 bit ripple counters.

9. Design and implementation of 3 bit synchronous counter

10. Design and implementation of shift registers

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3. SYLLABUS

UNIT IV SYNCHRONOUS SEQUENTIAL CIRCUITS DESIGN 9

Design of clocked sequential circuits - Moore/Mealy models, state minimization, state assignment, circuit implementation

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UNIT V MEMORY AND PROGRAMMABLE LOGIC DEVICES 9

Basic memory structure ROM: PROM – EPROM – EEPROM –RAM – Static and dynamic RAM – Programmable Logic Devices: Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Implementation of combinational logic circuits using PLA, PAL.

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TOTAL: 45 PERIODS (THEORY) + 30 PERIODS (LAB) = 75 PERIODS

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4. Course Outcomes

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After successful completion of the course, the students should be able to

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5. CO – PO /PSO Mapping

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6.1 LECTURE PLAN

UNIT 4: DESIGN OF CLOCKED SEQUENTIAL CIRCUITS

Total No. of Periods: 9

6.2. Activity Based Learning

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6.2. Activity Based Learning

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1. How many types of sequential circuits have?

a) 2

b) 5

c) 6

d) 7

Answer: a�Explanation: Two types of sequential circuirs are Moore and Mealy

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2. In Moore models, the output is the function of only

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a)present state

b)input state

c)next state

d) mid state�Answer: a�Explanation:In Moore Model, Output depends only on present state

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3. In Mealy models output are the functions of both

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a)present state

b)input state

c)next state

d) both a and b

Answer: d�Explanation:In Mealy Model, Output depends on present state and input.

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4. The behavior of sequential circuits is determined by the state of their

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a) clock

b) pulses

c)flip-flops

d) trigger

�Answer: c�Explanation: Sequential circuit is made of flip flops

Quiz

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5. A synchronous sequential circuit is made up of

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a)combinational gates

b) flip-flops

c) latches

d) both a and b

Answer: d�Explanation: A synchronous sequential circuit is made up of combinational circuits and flip flops

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6. The time sequence for flip-flop can be enumerated by

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a) state table

b) map

c) truth table

D ) graph

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Answer: a�Explanation:The time sequence for flip-flop can be enumerated by state table

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7. Synchronous sequential circuits that use clock are called

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1. clocked sequential circuits
2. sequential circuits
3. logic circuits
4. complex circuits

Answer: a �Explanation: Synchronous sequential circuits that use clock are called clocked sequential circuits

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8. Two states are said to be equal if they have the same

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1. inputs
2. next state
3. output
4. Both b and c

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Answer: d�Explanation: Two states are said to be equal if they have the same next state and output

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9. A decimal counter has ______ states.�a) 5�b) 10�c) 15�d) 20�

Answer: b�Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as Decade Counter counting from 0 to 9. 

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10. The negative transition in flip-flops are referred to as

1. clock
2. negative edge
3. positive edge
4. pulse transition

Answer: b�Explanation:The negative transition in flip-flops are referred to as negative edge

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11. The state diagram provides the same information as the

1. flip-flops provides
2. State table provides
3. truth table provides
4. latches

Answer: b�Explanation: The state diagram provides the same information as the State table provides

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12. A mod–n counter using asynchronous binary up–counter with clear input is shown in the figure. The value of n is_________.

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1. 5
2. 6
3. 7
4. 8

Answer: b�Explanation: When 0110 comes in the output, clear input is zero which clears the output to 0000.

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13. Three T flip flops are connected to form a counter. The maximum states possible for the counter will be:

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1. 5
2. 5
3. 7
4. 8�

Answer: d�Explanation: The maximum possible state in n-bit binary counter consisting of ‘n’ number of flip-flops is 2ⁿ.

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14. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

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1. input clock pulses are applied only to the first and last stages
2. input clock pulses are applied only to the last stage
3. input clock pulses are not used to activate any of the counter stages
4. input clock pulses are applied simultaneously to each stage

Answer: d

Explanation: In synchronous counters clock pulses are applied to all flip flops simultaneously

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15. In Sequential circuits the output states depend upon

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a) Past Input states�b) Present input states

c) Present as well as past input

d) None of the above

Answer: c�Explanation: In Sequential circuits the output states depend upon present and past inputs

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16. Sequential circuit contains

a) No memory element

b) Atleast one memory element

c) All inputs applied simultaneously�d) None of the above�

Answer: b�Explanation: Sequential circuit contains atleast one memory element.

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17. . The minimum number of flip flops required to construct a mod 64( divide by 64) ripple counter are

a) 4 flip flops�b) 5 flip flops�c) 6 flip flops�d) 64 flip flops

Answer: c�Explanation: The maximum possible state in n-bit binary counter consisting of ‘n’ number of flip-flops is 2ⁿ.

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18. . Mod 5 synchronous counter is designed using J-K flip flops, the number of count skipped by it will be

a) 2�b) 3

c) 4�d) 0��Answer: 3�Explanation: Mod 5 counter counts 000, 001,010, 011 and 100. So it skips 3 states viz 101, 110 and 111 

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19. The number of flip flops required for a mod 16 ring counter are

1. 4
2. 8
3. 10
4. 16

Answer: d�Explanation: The number of flip flops required for a mod n ring counter is n

20. The main difference between a register and a counter is ___________�a) A register has no specific sequence of states�b) A counter has no specific sequence of states�c) A register has capability to store one bit of information but counter has n-bit�d) A register counts data�

Answer: a�Explanation: The main difference between a register and a counter is that a register has no specific sequence of states except in certain specialized applications.

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21. A ripple counter's speed is limited by the propagation delay of:

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A. each flip-flop

B. all flip-flops and gates

C. the flip-flops only with gates

D. only circuit gates

Answer: A

Explanation : A ripple counter's speed is limited by the propagation delay of each flip-flop

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22. One of the major drawbacks to the use of asynchronous counters is that:

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A. low-frequency applications are limited because of internal propagation delays

B. high-frequency applications are limited because of internal propagation delays

C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

Answer: B

Explantion: A ripple counter's speed is limited by the propagation delay of each flip-flop

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23. A modulus-10 counter must have ________�a) 10 flip-flops�b) 4 Flip-flops�c) 2 flip-flops�d) Synchronous clocking

�Answer: b�Explanation: 2n-1 < = N < = 2n�For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we require 4 FFs.

Synchronous Sequential Circuits Analysis

Synchronous Sequential Circuit is analyzed and designed with the help of two models.

• 1. Mealy model
• 2. Moore model

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Qn.1 Analyze the given D Flip-flop equations:

D_A = xQ_A+ Q_B ; D_B = Q’_AQ_B

y = x’Q’_B + xQ_A

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Steps:

i) Determine FF input equations in terms of input variables and present state.

ii) Determine next state equation of FF using characteristic table.

iii) Determine circuit output if it is present.

Function Table

In function table, Next States are filled by using characteristic table of the corresponding FF.

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Characteristic Table

State Table

State table consists of present state, next state and output

State Table

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State Diagram

Qn.2 Analyze the given JK Flip-flop equations:

J_A = Q_B, K_A = X’Q_B, J_B = X’, K_B = X (XOR) Q_A

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Steps:

1. Determine FF input equations in terms of input variables and present state.
2. Determine next state equation of FF using characteristic table.
3. Determine circuit output if it is present.

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Logic Diagram

Transition Table

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Characteristic Table

State Table

In function table, Next States are filled by using characteristic table of the corresponding FF.

State table consists of present state, next state and output

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State Diagram

Procedure to construct State Diagram

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Mark Flip-flop states and connected them with directed line to next states using input and output values on the line.

Each row of the state table corresponds to a directed line.

Qn.3 Analyze the given T Flip-flop equations:

T_A = x, T_B = xQ_A, y = Q_AQ_B

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1. Determine FF input equations in terms of input variables and present state.
2. Determine next state equation of FF using characteristic table.
3. Determine circuit output if it is present.

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Logic Diagram

Function Table

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Characteristic Table

State Table

In function table, Next States are filled by using characteristic table of the corresponding FF.

State table consists of present state, next state and output

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State Diagram

Design of Clocked Synchronous Sequential Circuit

Design Procedure:

1. A state diagram is given which describes the behavior of the circuit that is to be designed.
2. Obtain the state table
3. Reduce the number of states by state reduction method, if required.
4. Do state assignment, if required.
5. Determine the FF required and assign the letter symbols
6. Decide the type of FF to be used.
7. Derive the circuit excitation table from the state table
8. Obtain the expression for circuit output and flip flop output
9. Implement the logic diagram

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Qn.1 Design the Synchronous Sequential Circuit for Melay state diagram using JK Flip-flop

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State Table

Excitation Table

Transition Table

K-Map for Flip-flops

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Qn.2 Design the Synchronous Sequential Circuit for Moore’s state diagram using JK Flip-flop

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State Table

Design Procedure:

1. A state diagram is given which describes the behavior of the circuit that is to be designed.
2. Obtain the state table
3. Reduce the number of states by state reduction method, if required.
4. Do state assignment, if required.
5. Determine the FF required and assign the letter symbols
6. Decide the type of FF to be used.
7. Derive the circuit excitation table from the state table
8. Obtain the expression for circuit output and flip flop output
9. Implement the logic diagram

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Excitation Table

Transition Table

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K-Map for J_B

K-Map for K_B

K-Map for J_A

K-Map for K_A

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State Reduction or State Minimisation, State Assignment

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Used to reduce the complexity of the sequential circuit.

State Diagram

State Table

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If the next state and output are same, eliminate the last state. Here, ‘e’ = ‘g’. Hence, reduce ‘g’ state. ‘g’ is replaced by ‘e’.

Here, ‘d’ = ‘f’. Hence, eliminate ‘f’ state. ‘f’ is replaced by ‘d’.

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Here, ‘d’ = ‘f’. Hence, eliminate ‘f’ state. ‘f’ is replaced by ‘d’.

Hence by using state reduction method, two states are reduced.

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Synchronous Counter

A counter is a register capable of counting the number of clock pulses arriving at its clock input.

Count represents the number of clock pulses arrived

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Qn. 1: Design a 3-bit synchronous counter using JK FF.

Step 1:

Find the number of FF required to build the counter.

FF required are 2ⁿ >= N

N-no of FFs; N- no of states. Here N = 8; n=3

3 FF’s needed in this design.

State Diagram

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Step 2: Write an Excitation Table of JK FF

Step 3:Determine Transition Table

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Step: 4 K-Map simplification for FF inputs

Step 5: Implement the counter

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Qn. 2: Design a synchronous Mod-6 counter using JK FF.

State Diagram

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Qn. 3: Design a synchronous decade counter using T FF.

State Diagram

Step 1:

Find the number of FF required to build the counter.

FF required are 2ⁿ>= N

N-no of FFs; N- no of states. Here N = 10; n=4 FF’s needed in this design

Step 2: Write an Excitation Table of T FF

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Step 3:Determine Transition Table

Step 4: K-Map Simplification

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Step 5: Implement counter

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Qn. 4: Design a synchronous Mod-5 counter using T FF.

State Diagram

Step 1:

Find the number of FF required to build the counter.

FF required are 2^n>= N

N-no of FFs; N- no of states. Here N = 5; n=3 FF’s needed in this design

Step 2: Write the T FF Excitation Table

Step 3: Determine the Transition Table

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Step 4: K-Map Simplification

Step 5: Implement counter

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Qn. 5: Design a synchronous counter to count the sequence 0,1,3,4,5,7,0,…using D FF.

State Diagram

Step 2: Write the T FF Excitation Table

Step 1:

Find the number of FF required to build the counter.

FF required are 2ⁿ>= N

N-no of FFs; N- no of states. Here N = 5; n=3 FF’s needed in this design

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Step 4: K-Map Simplification

Links to Videos and Learning Materials

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6.4: ASSIGNMENT

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6.5: Part-A: Q & A

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6.6: Part-B: Questions

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6.7: Supportive online Certification courses

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6.8 : Real time Applications in day to day life and to Industry

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MACHINE MOTION CONTROL:

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The most common and well known application of synchronous counters is machine motion control, the process in which the rotary shaft encoders convert the mechanical pulses into electric pulses. These pulses will act as clock input of the up/ down counter and will initiate the circuit motion.

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This circuit consists of photo transistor or light sensor and a LED connected to the rotor shaft. This arrangement is connected to the UP/ DOWN counter. When the machine started to move, it turns the encoder shaft by connecting and disturbing (making and breaking) the light beam between the light sensor and LED.

By this motion, the rotor creates clock pulses to increase the count of the up/ down counter circuit. So the counter note downs the motion of the shaft and gives the value that how much distance the rotor has moved.

To count the motion of the rotor shaft we increment the count by moving shaft in one direction and decrement the count by moving in another direction. We also use an encoder /decoder circuit to differentiate the direction of motion.

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Event Detectors:

Event detectors are the circuits which aid in determining the occurrence of a particular event. These devices are required to change their state when an event occurs and should further be held in the same state till that event gets cleared. Flip-flops are well-known to preserve their state until the appearance of a suitable condition at their inputs, which means they can act as event detectors. For example one can use a D flip-flop to detect the event of switching ‘on’ of the light, as shown in Figure .The working of such a circuit is explained in terms of wave forms shown by Figure.

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6.9: Content Beyond Syllabus

Sequence Generator

A sequence generator is a kind of digital logic circuit. The main function of it is to generate a set of outputs. Every output is one of a number of binary or Q-ary logic levels or symbols. The length of the series may be indefinite otherwise fixed. A special kind of sequence generator is a binary counter. These generators are utilized in a wide variety of applications like coding and control.

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Why Sequence Generator is Required?

The sequence generator circuit is used to generate a prescribed series of bits in synchronization through a CLK. This kind of generator is used as a code generator, counters, random bit generators, sequence, and prescribed period generator. The basic design diagram of this is shown below.

The N-bit shift register outputs like Q0 through QN-1 are applied like the inputs to a combinational circuit is known as the next state decoder. Here, the output of a next state decoder ‘Y’ is given as the serial input to the shift register. The designing of the next state decoder is done based on the sequence required.

Sequence Generator using Counters

The sequence generator block diagram using a counter is illustrated below. Here, the combinational circuit is the next state decoder. The input of this state decoder can be obtained from the outputs of the FFs. Similarly, the outputs of this state decoder are given as inputs to the flip-flops. Based on the number of FFs, the required sequence like 0’s or 1’s can be given and this can be generated like 1011011.

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The number of flip-flops can be decided through the given sequence like the following.:

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First, count the number of zeros and ones in the given sequence. Select the high number of the two. And let this number will be ‘N’. The no. of flip flops can be calculated as N = 2n-1

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For instance, the given sequence is 1011011, where the number of ones is 5 and the number of zeros is two. So choose a higher one from them that is 5. So 5 = 2n-1, so n=4 FFs will be necessary.

Steps Involved in Designing Sequence Generator using D Flip-Flops

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We know the function of a counter that allows an exact number of states in a prearranged sequence. For instance, an up-counter with 3-bit counts 0 to 7 whereas a similar order is upturned in the case of down counter.

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There are different ways to design the circuits can using FFs, multiplexers. Here we are designing a sequence generator using D FFs in different steps. Similarly, there are different steps involved in designing a sequence generator using JK Flip-Flops.

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Let’s take an example that we aim to design a circuit that moves throughout the states of 0-1-3-2 before doing again the similar pattern. The steps involved throughout this method are as follows.

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In Step-1

Firstly, we need to decide the no. of FFs which would be necessary to get our object. In the following example, there are four states which are equal to the 2-bit counter states excluding the order where they transfer. From this, one can estimate the necessity of FFs to be two in order to attain our object.

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In Step-2

From the step1, let’s design the state transition table for our sequence generator which is illustrated through the initial four columns in the table. In that, the primary two columns specify the present states and the next states. For example, in the first state of our example is “0 = 00” so it leads to the second state that is next state 1 = “01”.

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In Step-3

In the state transition table is extended by including the excitation table of the FFs. In this case, the excitation table of the D flip-flop is the fifth & the sixth columns of the table. For instance, look at the present and next states in the table like 1 & 0 respectively then it results ‘0’ in D1. In the following table, the first two columns represent the present state, the second two columns represent the next states and the last two are inputs of D-FF.

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In Step-4

In this step, the Boolean expressions for D0 & D1 can be derived with the help of a K-map. But this example is quite easy; so by using Boolean laws, we can solve for D1 & D0. Therefore

D0 = Q1’Q0’ + Q1’ Q0 = Q1’ (Q0’+Q0) = Q1’(1) = Q1’

D1 = Q1’Q0 + Q1 Q0 = Q0 (Q1’+Q1) = Q0 (1) = Q0

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In Step-5

The sequence generator can be designed using the D FFs based on inputs like the following:

In the above circuit, the preferred series is generated depending on the supplied CLK pulses. So it must be noted that the similarity existing here for an easy design can be successfully extended to produce a longer series of bits.

7. Assessment Schedule

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8. Prescribed Text Books & Reference Books

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TEXT BOOK:

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1. M. Morris Mano and Michael D. Ciletti, Digital Design, With an Introduction to the Verilog HDL, VHDL, and System Verilog, 6th Edition, Pearson, 2018.

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2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 5th Edition, Oxford University Press, 2018.

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REFERENCES:

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1. A.Anandkumar, Fundamental of digital circuits, 4th Edition, PHI Publication, 2016.

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2. William Kleitz, Digital Electronics -A Practical approach to VHDL, Prentice Hall

International Inc, 2012.

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3. Charles H. Roth, Jr. and Larry L. Kinney, Fundamentals of Logic Design, 7th Edition,Thomson Learning, 2014.

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4. Thomas L. Floyd, Digital Fundamentals, 11th Edition, Pearson Education Inc, 2017.

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5. John. M Yarbrough, Digital Logic: Applications and Design, 1st Edition, Cengage India, 2006.

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NPTEL LINK: https://nptel.ac.in/courses/108/105/108105132/

9. Mini-projects suggestions

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1. Gaming control

Many game shows use a circuit to determine which of the contestants ring in first. Design a circuit to determine which of two contestants rings in first. It has two inputs S1 and S0 which are connected to the contestants' buttons. The circuit has two outputs Z1 and Z0 which are connected to LED's to indicate which contestant rang in first. There is also a reset button that is used by the game show host to asynchronously reset the flip-flops to the initial state before each question. If contestant 0 rings in first, the circuit turns on LED 0. Once LED 0 is on, the circuit leaves it on regardless of the inputs until the circuit is asynchronously reset by the game show host. If contestant 1 rings in first, the circuit turns on LED 1 and leaves it on until the circuit is reset. If there is a tie, both LED's are turned on. The circuit requires four states: reset, contestant 0 wins, contestant 1 wins, and tie. One way to map the states is to use state 00 for reset, state 01 for contestant 0 wins, state 10 for contestant 1 wins, and state 11 for a tie. With this mapping, the outputs are equal to the current state, which simplifies the output equations.

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2. Traffic light controller

Design a simplified traffic-light controller that switches traffic lights on a crossing where a north-south (NS) street intersects an east-west (EW) street. The input to the controller is the WALK button pushed by pedestrians who want to cross the street. The outputs are two signals NS and EW that control the traffic lights in the Ns and EW directions. When NS or EW are 0, the red light is on, and when they are 1, the green light is on. When there are no pedestrians, NS=0, EW=1 for a minute, follow by NS=1 and EW=0 for 1 minutes, and so on, when WALK button is pushed, Ns and EW both become 0 for a minute when the present minute expires. After that the NS and EW signals continue alerting. For this traffic-light controller: a) Develop a state diagram. (Hint: can be done using 3 states) b) Draw the state transition table. c) Encode the states using minimum number of bits. d) Derive the logic schematic for a sequential circuit which implements the state transition table.

3. Bidirectional Visitor Counter

Display the number of students in the class. Whenever a student enters the class, an upcounter is activated and the display increases by 1. Whenever a student leaves the class, a down counter is activated and the display decreases by 1.

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4. Count the number of cars in a parking lot

Display the number of cars in the parking lot. Whenever a car enters the parking lot, an upcounter is activated and the display increases by 1. Whenever a car leaves the parking lot, a down counter is activated and the display decreases by 1.

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5. Automatic Washroom Light Switch

(https://www.electronicshub.org/automatic-washroom-light-switch/)

The reed switch is fixed to the wall near the door while the magnet is fixed to the door. This means that the reed switch will always be in closed state as the door is closed when the washroom is not in use (which is assumed as starting point) and the magnet will be near the switch. When the door is opened and then closed the door, this action will make the switch open (when the door is opened first) and close (when you close the door). As a result, the output of the Op-amp goes HIGH (when open the door) and then goes LOW (when close the door). This in turn will cause the counter to produce a HIGH output at its Pin 2. Since Pin 2 of CD4017 is connected to the relay, the light will be turned ON. While coming out, the door is once again opened and closed. This action will once again cause the same action i.e. switch will open and close and output of Op-Amp will become HIGH and then LOW. But, since the Pin 4 of CD4017 is connected to the Reset pin, all the outputs will become LOW and hence the relay will be turned OFF, which in turn switches off the light.

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6. Dancing LEDs

A group of 10 LEDs is connected to a 10 bit shift register. Whichever LED has to glow, then send 1 for others 0. Thus by sending different combinations of 1’s and 0’s the LEDs are made to glow in different fashion making them to dance.

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7. Digital Alarm

The clock is given in such a way that the 4 bit counter increases its count after 1 sec. After the counter counts 10, the buzzer will give alarm sound. Thus it produces a 10 sec alarm

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8. Design a traffic light

A traffic light is installed at a junction of a railroad and a road. The light is controlled by two switches in the rails placed 1 mile apart on either side of the junction. A switch is turned on when the train is over it and is turned off otherwise. The traffic light changes from green (logic 0) to red (logic 1) when the beginning of the train is 1 mile from the junction. The light changes back to green when the end of the train is 1 mile away from the junction. Assume that the length of the train is less then 2 miles. Obtain a primitive flow table for the circuit. Show that the flow table can be reduced to four rows. With further procedures implement the same.

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Disclaimer:��This document is confidential and intended solely for the educational purpose of RMK Group of Educational Institutions. If you have received this document through email in error, please notify the system manager. This document contains proprietary information and is intended only to the respective group / learning community as intended. If you are not the addressee you should not disseminate, distribute or copy through e-mail. Please notify the sender immediately by e-mail if you have received this document by mistake and delete this document from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited.

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Thank you