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Pins and Signals

8086 Microprocessor

Common signals

AD₀-AD₁₅ (Bidirectional)

Address/Data bus

Low order address bus; these are multiplexed with data.

When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A₀-A₁₅.

When data are transmitted over AD lines the symbol D is used in place of AD, for example D₀-D₇, D₈-D₁₅ or D₀-D₁₅.

A₁₆/S₃, A₁₇/S₄, A₁₈/S₅, A₁₉/S₆

High order address bus. These are multiplexed with status signals

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Pins and Signals

8086 Microprocessor

Common signals

BHE (Active Low)/S₇ (Output)

Bus High Enable/Status

It is used to enable data onto the most significant half of data bus, D₈-D₁₅. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S₇.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.

It is active when low.

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Pins and Signals

8086 Microprocessor

Common signals

READY

This is the acknowledgement from the slow device or memory that they have completed the data transfer.

The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086.

The signal is active high.

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Pins and Signals

8086 Microprocessor

Common signals

RESET (Input)

Causes the processor to immediately terminate its present activity.

The signal must be active HIGH for at least four clock cycles.

CLK

The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.

This signal is active high and internally synchronized.

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Pins and Signals

8086 Microprocessor

Min/ Max Pins

The 8086 microprocessor can work in two modes of operations : Minimum mode and Maximum mode.

In the minimum mode of operation the microprocessor do not associate with any co-processors and can not be used for multiprocessor systems.

In the maximum mode the 8086 can work in multi-processor or co-processor configuration.

Minimum or maximum mode operations are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in minimum mode otherwise it operates in Maximum mode.

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Pins and Signals

8086 Microprocessor

	(Data Transmit/ Receive) Output signal from the processor to control the direction of data flow through the data transceivers

	(Data Enable) Output signal from the processor used as out put enable for the transceivers

ALE	(Address Latch Enable) Used to demultiplex the address and data lines using external latches

	Used to differentiate memory access and I/O access. For memory reference instructions, it is high. For IN and OUT instructions, it is low.

	Write control signal; asserted low Whenever processor writes data to memory or I/O port

	(Interrupt Acknowledge) When the interrupt request is accepted by the processor, the output is low on this line.

Minimum mode signals

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Pins and Signals

8086 Microprocessor

HOLD	Input signal to the processor form the bus masters as a request to grant the control of the bus. Usually used by the DMA controller to get the control of the bus.

HLDA	(Hold Acknowledge) Acknowledge signal by the processor to the bus master requesting the control of the bus through HOLD. The acknowledge is asserted high, when the processor accepts HOLD.

Minimum mode signals

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Pins and Signals

8086 Microprocessor

	Status signals; used by the 8086 bus controller to generate bus timing and control signals. These are decoded as shown.

Maximum mode signals

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Pins and Signals

8086 Microprocessor

	(Queue Status) The processor provides the status of queue in these lines. The queue status can be used by external device to track the internal status of the queue in 8086. The output on QS₀ and QS₁ can be interpreted as shown in the table.

Maximum mode signals

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Pins and Signals

8086 Microprocessor

Maximum mode signals

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Architecture

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Architecture

8086 Microprocessor

Execution Unit (EU)

EU executes instructions that have already been fetched by the BIU.

BIU and EU functions separately.

Bus Interface Unit (BIU)

BIU fetches instructions, reads data from memory and I/O ports, writes data to memory and I/ O ports.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Dedicated Adder to generate 20 bit address

Four 16-bit segment registers

Code Segment (CS)

Data Segment (DS)

Stack Segment (SS)

Extra Segment (ES)

Segment Registers >>

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

8086’s 1-megabyte memory is divided into segments of up to 64K bytes each.

Programs obtain access to code and data in the segments by changing the segment register content to point to the desired segments.

The 8086 can directly address four segments (256 K bytes within the 1 M byte of memory) at a particular time.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

Code Segment Register

16-bit

CS contains the base or start of the current code segment; IP contains the distance or offset from this address to the next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically shifting the contents of CS 4-bits to the left and then adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the contents of the CS register multiplied by 16 and then offset is added provided by the IP.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

Data Segment Register

16-bit

Points to the current data segment; operands for most instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit displacement are used as offset for computing the 20-bit physical address.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

Stack Segment Register

16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer (SP) for stack instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack address is calculated from the Stack segment (SS) and the Base Pointer (BP).

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

Extra Segment Register

16-bit

Points to the extra segment in which data (in excess of 64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-bit physical address for the destination.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

Segment

Registers

Instruction Pointer

16-bit

Always points to the next instruction to be executed within the currently executing code segment.

So, this register contains the 16-bit offset address pointing to the next instruction code within the 64Kb of the code segment area.

Its content is automatically incremented as the execution of the next instruction takes place.

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Architecture

8086 Microprocessor

Bus Interface Unit (BIU)

A group of First-In-First-Out (FIFO) in which up to 6 bytes of instruction code are pre fetched from the memory ahead of time.

This is done in order to speed up the execution by overlapping instruction fetch with execution.

This mechanism is known as pipelining.

Instruction queue

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Architecture

8086 Microprocessor

Some of the 16 bit registers can be used as two 8 bit registers as :

AX can be used as AH and AL

BX can be used as BH and BL

CX can be used as CH and CL

DX can be used as DH and DL

Execution Unit (EU)

EU decodes and executes instructions.

A decoder in the EU control system translates instructions.

16-bit ALU for performing arithmetic and logic operation

Four general purpose registers(AX, BX, CX, DX);

Pointer registers (Stack Pointer, Base Pointer);

and

Index registers (Source Index, Destination Index) each of 16-bits

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Architecture

8086 Microprocessor

Registers

Accumulator Register (AX)

Consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word, and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or AL.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Registers

Base Register (BX)

Consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word, and BH contains the high-order byte.

This is the only general purpose register whose contents can be used for addressing the 8086 memory.

All memory references utilizing this register content for addressing use DS as the default segment register.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Registers

Counter Register (CX)

Consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a counter.

Execution Unit (EU)

Example:

The instruction LOOP START automatically decrements CX by 1 without affecting flags and will check if [CX] = 0.

If it is zero, 8086 executes the next instruction; otherwise the 8086 branches to the label START.

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Architecture

8086 Microprocessor

Registers

Execution Unit (EU)

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Architecture

8086 Microprocessor

Registers

Stack Pointer (SP) and Base Pointer (BP)

SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during execution of instructions that involve the stack segment in the external memory.

SP contents are automatically updated (incremented/ decremented) due to execution of a POP or PUSH instruction.

BP contains an offset address in the current SS, which is used by instructions utilizing the based addressing mode.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Registers

Source Index (SI) and Destination Index (DI)

Used in indexed addressing.

Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Registers

Source Index (SI) and Destination Index (DI)

Used in indexed addressing.

Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Flag Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OF	DF	IF	TF	SF	ZF		AF		PF		CF

Carry Flag

This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction.

Parity Flag

This flag is set to 1, if the lower byte of the result contains even number of 1’s ; for odd number of 1’s set to zero.

Auxiliary Carry Flag

This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.

Zero Flag

This flag is set, if the result of the computation or comparison performed by an instruction is zero

Sign Flag

This flag is set, when the result of any computation is negative

Tarp Flag

If this flag is set, the processor enters the single step execution mode by generating internal interrupts after the execution of each instruction

Interrupt Flag

Causes the 8086 to recognize external mask interrupts; clearing IF disables these interrupts.

Direction Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the string is processed beginning from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto incrementing mode.

Over flow Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow will be set.

Execution Unit (EU)

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Architecture

8086 Microprocessor

Sl.No.	Type	Register width	Name of register
1	General purpose register	16 bit	AX, BX, CX, DX
1	General purpose register	8 bit	AL, AH, BL, BH, CL, CH, DL, DH
2	Pointer register	16 bit	SP, BP
3	Index register	16 bit	SI, DI
4	Instruction Pointer	16 bit	IP
5	Segment register	16 bit	CS, DS, SS, ES
6	Flag (PSW)	16 bit	Flag register

8086 registers categorized into 4 groups

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OF	DF	IF	TF	SF	ZF		AF		PF		CF

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Architecture

8086 Microprocessor

Register	Name of the Register	Special Function
AX	16-bit Accumulator	Stores the 16-bit results of arithmetic and logic operations
AL	8-bit Accumulator	Stores the 8-bit results of arithmetic and logic operations
BX	Base register	Used to hold base value in base addressing mode to access memory data
CX	Count Register	Used to hold the count value in SHIFT, ROTATE and LOOP instructions
DX	Data Register	Used to hold data for multiplication and division operations
SP	Stack Pointer	Used to hold the offset address of top stack memory
BP	Base Pointer	Used to hold the base value in base addressing using SS register to access data from stack memory
SI	Source Index	Used to hold index value of source operand (data) for string instructions
DI	Data Index	Used to hold the index value of destination operand (data) for string operations

Registers and Special Functions

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ADDRESSING MODES

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Addressing Modes

Group I : Addressing modes for register and immediate data

Group IV : Relative Addressing mode

Group V : Implied Addressing mode

Group III : Addressing modes for I/O ports

Group II : Addressing modes for memory data

8086 Microprocessor

Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted in an instruction are known as addressing modes.

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

The instruction will specify the name of the register which holds the data to be operated by the instruction.

Example:

MOV CL, DH

The content of 8-bit register DH is moved to another 8-bit register CL

(CL) ← (DH)

Group I : Addressing modes for register and immediate data

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

In immediate addressing mode, an 8-bit or 16-bit data is specified as part of the instruction

Example:

MOV DL, 08H

The 8-bit data (08_H) given in the instruction is moved to DL

(DL) ← 08_H

MOV AX, 0A9FH

The 16-bit data (0A9F_H) given in the instruction is moved to AX register

(AX) ← 0A9F_H

Group I : Addressing modes for register and immediate data

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Addressing Modes : Memory Access

8086 Microprocessor

Physical Address (20 Bits)

Adder

Segment Register (16 bits)

0 0 0 0

Offset Value (16 bits)

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Addressing Modes : Memory Access

8086 Microprocessor

20 Address lines ⇒ 8086 can address up to 2²⁰ = 1M bytes of memory�
However, the largest register is only 16 bits

Physical Address will have to be calculated Physical Address : Actual address of a byte in memory. i.e. the value which goes out onto the address bus.

Memory Address represented in the form – Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access memory, it takes the contents of a segment register, shifts it one hexadecimal place to the left (same as multiplying by 16₁₀), then add the required offset to form the 20- bit address

89AB : F012 → 89AB → 89AB0 (Paragraph to byte → 89AB x 10 = 89AB0)

F012 → 0F012 (Offset is already in byte unit)

+ -------

98AC2 (The absolute address)

16 bytes of contiguous memory

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Addressing Modes : Memory Access

8086 Microprocessor

To access memory we use these four registers: BX, SI, DI, BP�
Combining these registers inside [ ] symbols, we can get different memory locations (Effective Address, EA)

Supported combinations:

[BX + SI]�[BX + DI]�[BP + SI]�[BP + DI]�	[SI]�[DI]�d16 (variable offset only)�[BX]	[BX + SI + d8]�[BX + DI + d8]�[BP + SI + d8]�[BP + DI + d8]�
[SI + d8]�[DI + d8]�[BP + d8]�[BX + d8]�	[BX + SI + d16]�[BX + DI + d16] �[BP + SI + d16]�[BP + DI + d16]�	[SI + d16]�[DI + d16]�[BP + d16]�[BX + d16]

BX BP	SI DI	+ disp

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

Here, the effective address of the memory location at which the data operand is stored is given in the instruction.

The effective address is just a 16-bit number written directly in the instruction.

Example:

MOV BX, [1354H]

MOV BL, [0400H]

The square brackets around the 1354_H denotes the contents of the memory location. When executed, this instruction will copy the contents of the memory location into BX register.

This addressing mode is called direct because the displacement of the operand from the segment base is specified directly in the instruction.

Group II : Addressing modes for memory data

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

In Register indirect addressing, name of the register which holds the effective address (EA) will be specified in the instruction.

Registers used to hold EA are any of the following registers:

BX, BP, DI and SI.

Content of the DS register is used for base address calculation.

Example:

MOV CX, [BX]

Operations:

EA = (BX)

BA = (DS) x 16₁₀

MA = BA + EA

(CX) ← (MA) or,

(CL) ← (MA)

(CH) ← (MA +1)

Group II : Addressing modes for memory data

Note : Register/ memory enclosed in brackets refer to content of register/ memory

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

In Based Addressing, BX or BP is used to hold the base value for effective address and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction.

In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value.

When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS.

When BP holds the base value of EA, BP and SS is used.

Example:

MOV AX, [BX + 08H]

Operations:

0008_H ← 08_H (Sign extended)

EA = (BX) + 0008_H

BA = (DS) x 16₁₀

MA = BA + EA

(AX) ← (MA) or,

(AL) ← (MA)

(AH) ← (MA + 1)

Group II : Addressing modes for memory data

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

SI or DI register is used to hold an index value for memory data and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction.

Displacement is added to the index value in SI or DI register to obtain the EA.

In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value.

Example:

MOV CX, [SI + 0A2H]

Operations:

FFA2_H ← A2_H (Sign extended)

EA = (SI) + FFA2_H

BA = (DS) x 16₁₀

MA = BA + EA

(CX) ← (MA) or,

(CL) ← (MA)

(CH) ← (MA + 1)

Group II : Addressing modes for memory data

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

In Based Index Addressing, the effective address is computed from the sum of a base register (BX or BP), an index register (SI or DI) and a displacement.

Example:

MOV DX, [BX + SI + 0AH]

Operations:

000A_H ← 0A_H (Sign extended)

EA = (BX) + (SI) + 000A_H

BA = (DS) x 16₁₀

MA = BA + EA

(DX) ← (MA) or,

(DL) ← (MA)

(DH) ← (MA + 1)

Group II : Addressing modes for memory data

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

Employed in string operations to operate on string data.

The effective address (EA) of source data is stored in SI register and the EA of destination is stored in DI register.

Segment register for calculating base address of

source data is DS and that of the destination data is ES

Example: MOVS BYTE

Operations:

Calculation of source memory location:

EA = (SI) BA = (DS) x 16₁₀ MA = BA + EA

Calculation of destination memory location:

EA_E = (DI) BA_E = (ES) x 16₁₀MA_E = BA_E + EA_E

(MAE) ← (MA)

If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1

If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI) + 1

Group II : Addressing modes for memory data

Note : Effective address of the Extra segment register

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

These addressing modes are used to access data from standard I/O mapped devices or ports.

In direct port addressing mode, an 8-bit port address is directly specified in the instruction.

Example: IN AL, [09H]

Operations: PORT_addr = 09_H

(AL) ← (PORT)

Content of port with address 09_H is moved to AL register

In indirect port addressing mode, the instruction will specify the name of the register which holds the port address. In 8086, the 16-bit port address is stored in the DX register.

Example: OUT [DX], AX

Operations: PORT_addr = (DX)

(PORT) ← (AX)

Content of AX is moved to port whose address is specified by DX register.

Group III : Addressing modes for I/O ports

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

In this addressing mode, the effective address of a program instruction is specified relative to Instruction Pointer (IP) by an 8-bit signed displacement.

Example: JZ 0AH

Operations:

000A_H ← 0A_H (sign extend)

If ZF = 1, then

EA = (IP) + 000A_H

BA = (CS) x 16₁₀

MA = BA + EA

If ZF = 1, then the program control jumps to new address calculated above.

If ZF = 0, then next instruction of the program is executed.

Group IV : Relative Addressing mode

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Addressing Modes

8086 Microprocessor

Immediate Addressing

Direct Addressing

Based Addressing

Indexed Addressing

Based Index Addressing

String Addressing

Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

Instructions using this mode have no operands. The instruction itself will specify the data to be operated by the instruction.

Example: CLC

This clears the carry flag to zero.

Group IV : Implied Addressing mode