OCP NIC Community Update�March 2025

�����Sub-group Project wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

Agenda

• Proposed specification updates/clarifications
• Thermal Workstream Updates
• Signal Integrity Compliance Test Fixtures
• Thermal Compliance Test Fixtures

Electrical Spec Updates

• Electrical updates and additions for version 1.6.0

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• Refer to Feb 2025 slides for previously noted changes

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• Latest draft spec available for review (shortly)

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• Targeting version 1.6.0 for the end of March 2025

Section 4.5.2.3 - BIF# pins

• Clarified the BIF# pin encodings in the spec and associated bifurcation spreadsheet

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• Values represent the electrical high/low voltage levels

Section 5.10.3.x OEM Record Changes

• Global Type ID update

0xC1 → 0xD2 (DSFF OEM Record)

0xC2 → 0xD3 (Flex I/O OEM Record)

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• Prevent Type ID collisions with existing MHS specifications.

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• Type ID allocations to be managed by MHS in Spreadsheet/GitHub
• (From 3/5/2025 Call - Are there opportunities to consolidate the 0xD2/0xD3 records? Rename “DSFF OEM Record” to “Extended OEM Record”? Concern raised about only 63 record entries permissible between 0xC0 and 0xFF.�
• Clarified OEM Record byte ordering for multi-byte entries
• Editorial change only; no definition change.

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Section 5.10.3.1 0xC0 Record Changes

• Offset 3 -
• Add encoding for version 1.6.0

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• Offset 21 - Transceiver Reference Power Level
• Value used for thermal tier determination
• Proposed framework less tied to transceiver type
• Can accommodate future transceivers

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• Better alignment to predefined SFP/QSFP/OSFP spec power levels
• Should we explicitly declare the Transceiver Reference Power Level instead of the Power Class?
• Use encoding 0xFE to look at Offset 29 for transceivers outside of predefined values
• (From 3/5/2025 Call - Remove power classes all together, use same encoding as Offset 29)

Section 5.10.3.1 0xC0 Record Changes

• Offset 29 - Max Supported Power for Transceivers
• Proposed new field (was reserved)
• Defines maximum board level transceiver power
• 0.25 W resolution
• Agnostic to transceiver type

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• Is it useful to have both Offset 21 and 29?
• Or should we merge them?
• (From 3/5/2025 Call - Keep these separate)

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Section 5.10.3.2 0xD0 Record Changes

• PCIe Mode Descriptor
• Clarified value of Offset 1 (Number of Supported PCIe links in PCIe Mode)
• “1” - single link
• “2” - two links
• “4” - four links
• “n” - n links

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• (From 3/5/2025 Call - Remove text “x2 and x1 NIC endpoint links are not supported” – it’s supported)

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Section 5.10.3.4 0xD2 Record Changes

• DSFF OEM Record
• This was Record 0xC1 in version 1.5.0
• Proposed move to 0xD2 to prevent incompatibilities with MHS M-PNP spec.

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• Offset 3 - OEM Record Version
• Add encoding for 1.6.0

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Section 5.10.3.4 0xD3 Record Changes

• Flex I/O OEM Record
• This was Record 0xC2 in version 1.5.0
• Proposed move to 0xD3 to prevent incompatibilities with MHS M-PNP spec.

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• Offset 3 - OEM Record Version
• Add encoding for 1.6.0

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• Offset 4 - Flex I/O Mode support
• Clarified card defaults to RBT mode if RBT and Time Sync are supported.

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• (From 3/5/2025 Call - Switching from RBT to Timing Sync Mode is outside the scope of this spec; likely a DMTF/PCI-SIG type of external specification. Generally expect cards to design-in one interface or the other.)

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Section 5.10.3.4 0xD3 Record Questions

• Offset 11 through 21+(2*n) - Timing Interface Propagation Delay
• BMC reads FRU
• How are these consumed at the software level?

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• Are these values passed between the management entity and the SW stack?

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• What if the board DPLL can account for propagation deltas between the interface?
• (e.g between TS_RX_FREQ, TS_RX_SYNC)
• How would this be encoded?

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• Are these “FYI” values only?

SFF-TA-1002 Power Excursions

• Work in progress by SFF-TA-TWG
• Includes power excursion text - similar to CEM.
• Please review

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• Draft 1.5.1 available for review on the SNIA portal (membership required to download)
• https://members.snia.org/wg/sfftwg/document/27935

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• No power excursion changes to the OCP NIC specification at this time.

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• (From 3/5/2025 Call - We’ll follow up in the OCP NIC workstream once SNIA publishes the update. For now, SNIA member companies should review proposal.)

Thermal Workstream Update

• DSFF Thermal Test Fixture
• Fixture will utilize removable blocks as blockage in top of chamber
• Community has requested other configuration options still be present in design
• Dummy PCIe card blockage (like in SFF TFF)
• Two cards stacked on top of each other (like in TSFF TFF)

Thermal Workstream Update

• 1U height option for SFF and DSFF
• Easiest path to cool the high power to their max capabilities
• Early thermal simulations show promising results

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• Thermal workstream meets every other Thursday at 9am PST
• Next meeting will be 3/6
• Email to be added: joseph.s.hanson@intel.com

DSFF SI Update

• Dell contributing DSFF CBB SI fixture, Gen 6 by default
• Initial protos arrived in Nov 2024
• Several issues found, addressed in next revision

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• Next prototype gerber sent for fabrication
• Schematic & Board files here: Link
• Proto assembly complete est: est Mar 24th
• Broadcom, Dell, Intel lined up to test

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• For DSFF CLB use two of CLB SFFs

DSFF Thermal Test Fixture Overview

• New DSFF TTF will support SFF / TSFF / DSFF form factors at PCIe^® speeds up to Gen 7

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• Metal housing with a PCB designed to extend PCIe lanes from a DC-MHS compatible server to a mounted OCP 3.0 DUT card

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• Intended to attach to a wind tunnel or flow bench

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• Pre-defined sensor locations for test repeatability

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• Onboard MCU shall operate same as prior thermal test fixtures and codebase will be uploaded to the Github repository

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• Schematic & ECAD complete, uploaded to the OCP NIC Cloud

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• Assembly complete Est March 31st

DSFF Thermal Test Fixture

DSFF TTF Airflow Operation

Please note: PCIE^® design mark is a registered

trademark and/or service mark of PCI-SIG.

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Thank You

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