Crossing-Free�Boundary Labeling�Using Hyperleaders
Chun-Cheng Lin
Taipei Municipal University of Education
Outline
2
Map Labeling
3
Boundary Labeling [Bekos et al., GD 2004]
4
(Bekos & Symvonis, GD 2005)
Min (total leader length)
s.t. #(leader crossing) = 0
1-side, 2-side, 4-side
site
label
leader
Variants
5
5
Many-Site-to-One-Label Boundary Labeling�(a.k.a., Many-to-One Boundary Labeling)�(Lin, Kao Yen, 2008)
6
Brown booby
Taiwan hill partridge
Masked palm civet
Hawk
Melogale moschata
Bamboo partridge
Chinese pangolin
Mallard
Distribution of some
animals in Taiwan:
Legend:
Brown booby
Taiwan hill partridge
Masked palm civet
Hawk
Melogale moschata
Bamboo partridge
Chinese pangolin
Mallard
Two-Side Many-to-One Boundary Labeling
7
Brown booby
Masked palm civet
Hawk
Chinese pangolin
Taiwan hill partridge
Melogale moschata
Bamboo partridge
Mallard
One More Example�– Server Motherboard –
8
8 DIMMs
ATX Power Supply
2 LAN Ports
Battery
BIOS
2 Chipsets
6 SATA Connectors
IDE Slot
PS2 Port
USB Port
COM Port
VGA Port
4 CPUs
6 Expansion Slots
Many-to-One Boundary Labeling�Using Hyperleaders & Dummy Labels
9
R
Track Routing Area
l1’
l1
l2
No leader crossings
adding
dummy
labels
R
l1
Track Routing Area
l2
hyper-leader
dummy
label
Our Concerned Problem
s.t. there are no leader crossings.
Furthermore, after determining # & pos of dummy labels,
the number of bends is minimized;
the total leader length is minimized.
10
R
Our Theoretical Results for Many-to-One Boundary Labeling
11
objective | # of sides | leader type | complexity | solution |
Min #(crossing) | 1-side | opo | NP-complete | 3-approx. |
2-side | opo | NP-complete | 3(1+.301/c)-approx. | |
1-side | po | NP-complete | heuristic | |
2-side | po | NP-complete | heuristic | |
Min Total leader length | any | any | polynomial time | |
Min #(dummy labels) | 1-side | opo | O(n log n) | |
2-side | opo | O(n2) | ||
Note that c is a number depending on the sum of edge weights.
12
R
R
R
g1
g2
g3
g4
g5
g6
g7
g8
R
g1
g2
g3
g4
g5
g6
g7
g8
l1
l2
l3
l4
l5
l6
l7
l8
One-Side Case
Input
Step 1.
Step 2.
Observation. Only the order of y-coordinates of sites matters.
Step 3.
How to Route Hyperleaders?
13
ε
R
gi
li-1
li
R
gi
li-1
li
yp(li)
R
gi
li
li+1
yp(li)
R
gi
li
R
gi
li
ε
yp(li)
Push i to stack S.
(the routing of gi is determined after the routing of gi+1 is determined)
R
gi
li
li+1
yp(li)
R
ε
gi
li
li+1
ε
R
gi
li-1
li
R
gi
li-1
li
yp(li)
ε
R
gi
li
li+1
ε
Two-Side Case
L
Step 1.
Step 2.
R
Scan from the top to the bottom.
Each label is placed on the right
or the left line.
If moving labels in L to R does not result in any dummy label, the concerned label is placed on the same line as its guy; o.w. ...
its recently
shown guy.
the concerned label
R
g1
g2
g3
g4
g5
g6
g7
g8
14
An Example
15
R
Move to the same side of its recently
shown guy, if no crossing.
Make the numbers of components
on both sides as equal as possible
An Example (cont.)
16
R
Many-to-One Boundary Labeling
17
8 DIMMs
ATX Power Supply
2 LAN Ports
Battery
BIOS
2 Chipsets
6 SATA
IDE Slot
PS2 Port
USB Port
COM Port
VGA Port
4 CPUs
6 Expansion
6 SATA
2 CPUs
2 DIMMs
ATX Power Supply
Battery
BIOS
2 Chipsets
6 DIMMs
IDE Slot
PS2 Port
6 DIMMs
COM Port
VGA Port
2 LAN Ports
6 Expansion
2 CPUs
Our Results
18
objective | # of sides | leader type | Complexity* |
Minimize #(dummy nodes) | 1-side | opo | O(n log n) |
2-side | opo | O(n2) |
* Note that n is the number of sites.
Four-side case
19
Simulated Annealing for 4-side case
20
p
A1
A2
A3
A4
p
λ (normalized # of dummy labels) + (1-λ)(normalized total leader length)
c
Statistics
21
Experimental Results (I)
22
Experimental Results (II)
23
A Practical Example
24
Conclusion
25
6 SATA
2 CPUs
2 DIMMs
ATX Power Supply
Battery
BIOS
2 Chipsets
6 DIMMs
IDE Slot
PS2 Port
6 DIMMs
COM Port
VGA Port
2 LAN Ports
6 Expansion
2 CPUs
Future work
26
R
l1
l2
l3
l4
l5
R
l1
l2
l3
l4
l5
R
l1
l2
l3
l4
l5
MST
Steiner Tree
Steiner
points
Thank you for your attention!