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Crossing-Free�Boundary Labeling�Using Hyperleaders

Chun-Cheng Lin

Taipei Municipal University of Education

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Outline

  • Introduction

  • Motivations

  • Our results
    • One-side case 🡪 O(n log n) time solvable
    • Two-side case 🡪 O(n2) time solvable
    • Four-side case 🡪 simulated annealing

  • Conclusion & Future work

2

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Map Labeling

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  • Point features
    • e.g., city

  • Line features
    • e.g., river

  • Area features
    • e.g., mountain

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Boundary Labeling [Bekos et al., GD 2004]

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(Bekos & Symvonis, GD 2005)

  • Type-opo leaders
  • Type-po leders

  • Type-s leaders

Min (total leader length)

s.t. #(leader crossing) = 0

1-side, 2-side, 4-side

site

label

leader

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Variants

  • Polygons labeling

  • Multi-stack boundary labeling

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  • Type-od leader

  • Type-pd leader
  • Type-do leader

5

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Many-Site-to-One-Label Boundary Labeling�(a.k.a., Many-to-One Boundary Labeling)�(Lin, Kao Yen, 2008)

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Brown booby

Taiwan hill partridge

Masked palm civet

Hawk

Melogale moschata

Bamboo partridge

Chinese pangolin

Mallard

Distribution of some

animals in Taiwan:

Legend:

Brown booby

Taiwan hill partridge

Masked palm civet

Hawk

Melogale moschata

Bamboo partridge

Chinese pangolin

Mallard

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Two-Side Many-to-One Boundary Labeling

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Brown booby

Masked palm civet

Hawk

Chinese pangolin

Taiwan hill partridge

Melogale moschata

Bamboo partridge

Mallard

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One More Example�– Server Motherboard –

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8 DIMMs

ATX Power Supply

2 LAN Ports

Battery

BIOS

2 Chipsets

6 SATA Connectors

IDE Slot

PS2 Port

USB Port

COM Port

VGA Port

4 CPUs

6 Expansion Slots

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Many-to-One Boundary Labeling�Using Hyperleaders & Dummy Labels

  • Type-opo hyperleaders & dummy labels

  • Main features
    • No confusion and crossings between leaders
    • Suitable for labeling the sites with clusters
    • One-side and two-side cases are suitable for the maps with vertical-strip shapes

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R

Track Routing Area

l1

l1

l2

No leader crossings

adding

dummy

labels

R

l1

Track Routing Area

l2

hyper-leader

dummy

label

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Our Concerned Problem

  • Minimizing the number of dummy labels

s.t. there are no leader crossings.

Furthermore, after determining # & pos of dummy labels,

the number of bends is minimized;

the total leader length is minimized.

10

R

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Our Theoretical Results for Many-to-One Boundary Labeling

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objective

# of sides

leader type

complexity

solution

Min #(crossing)

1-side

opo

NP-complete

3-approx.

2-side

opo

NP-complete

3(1+.301/c)-approx.

1-side

po

NP-complete

heuristic

2-side

po

NP-complete

heuristic

Min

Total leader length

any

any

polynomial time

Min

#(dummy labels)

1-side

opo

O(n log n)

2-side

opo

O(n2)

Note that c is a number depending on the sum of edge weights.

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12

R

R

R

g1

g2

g3

g4

g5

g6

g7

g8

R

g1

g2

g3

g4

g5

g6

g7

g8

l1

l2

l3

l4

l5

l6

l7

l8

One-Side Case

Input

Step 1.

Step 2.

Observation. Only the order of y-coordinates of sites matters.

Step 3.

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How to Route Hyperleaders?

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ε

R

gi

li-1

li

R

gi

li-1

li

yp(li)

R

gi

li

li+1

yp(li)

R

gi

li

R

gi

li

ε

yp(li)

Push i to stack S.

(the routing of gi is determined after the routing of gi+1 is determined)

R

gi

li

li+1

yp(li)

R

ε

gi

li

li+1

ε

R

gi

li-1

li

R

gi

li-1

li

yp(li)

ε

R

gi

li

li+1

ε

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Two-Side Case

L

Step 1.

Step 2.

R

Scan from the top to the bottom.

Each label is placed on the right

or the left line.

If moving labels in L to R does not result in any dummy label, the concerned label is placed on the same line as its guy; o.w. ...

its recently

shown guy.

the concerned label

R

g1

g2

g3

g4

g5

g6

g7

g8

14

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An Example

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R

Move to the same side of its recently

shown guy, if no crossing.

Make the numbers of components

on both sides as equal as possible

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An Example (cont.)

16

R

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Many-to-One Boundary Labeling

  • The original

  • New

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8 DIMMs

ATX Power Supply

2 LAN Ports

Battery

BIOS

2 Chipsets

6 SATA

IDE Slot

PS2 Port

USB Port

COM Port

VGA Port

4 CPUs

6 Expansion

6 SATA

2 CPUs

2 DIMMs

ATX Power Supply

Battery

BIOS

2 Chipsets

6 DIMMs

IDE Slot

PS2 Port

6 DIMMs

COM Port

VGA Port

2 LAN Ports

6 Expansion

2 CPUs

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Our Results

18

objective

# of sides

leader type

Complexity*

Minimize

#(dummy nodes)

1-side

opo

O(n log n)

2-side

opo

O(n2)

* Note that n is the number of sites.

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Four-side case

  • [Bekos et al., 2007]
    • Determining which sites are connected to one of the four sides so that the objective is achieved leads to the NP-hard Partition problem

  • Use the simulated annealing (SA) to solve the four-side case

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Simulated Annealing for 4-side case

  • Configuration
    • Corresponded to a site p
    • Site p divides the map into four regions A1-A4

  • Initial configuration
    • A configuration where the sites in each region are as equal as possible

  • Neighbor
    • Randomly select a corner c of the map
    • Rotate the line connected to c around c in counterclockwise direction
    • The configuration corresponding to the first scanned site is selected as the neighbor

  • Energy cost function =

  • The cooling schedule is based on the previous work

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p

A1

A2

A3

A4

p

λ (normalized # of dummy labels) + (1-λ)(normalized total leader length)

c

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Statistics

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Experimental Results (I)

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Experimental Results (II)

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A Practical Example

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Conclusion

  • Crossing-free many-to-one boundary labeling using hyperleaders (and dummy labels)
    • 1-side case 🡪 O(n log n) time for dummy label min. problem
    • 2-side case 🡪 O(n2) time for dummy label min. problem
    • 4-side case 🡪 simulated annealing

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6 SATA

2 CPUs

2 DIMMs

ATX Power Supply

Battery

BIOS

2 Chipsets

6 DIMMs

IDE Slot

PS2 Port

6 DIMMs

COM Port

VGA Port

2 LAN Ports

6 Expansion

2 CPUs

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Future work

  • Considering other kinds of leaders

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R

l1

l2

l3

l4

l5

R

l1

l2

l3

l4

l5

R

l1

l2

l3

l4

l5

MST

Steiner Tree

Steiner

points

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Thank you for your attention!