Abstract and Bio

Learn how computers work between silicon and assembly — Build a CPU with Python��2018-12-11 @ CARPE Dec Meeting, Columbus, Ohio��Programming languages are designed for a specific level of abstraction or distance from the hardware. The main trade off is "developer productivity" vs "control over hardware". C and assembly are low level and therefore map closely to CPU instructions. Python on the other hand goes through many layers, libraries, and a virtual machine before the CPU is reached. This allows powerful programs to be written concisely and cross-platform—but it also conceals the true nature at the heart of our modern world. Unveiling the magic within can lead to interesting insights about how computing got to where it is today.��We will build up CPU focused on transparency, interactivity, and modularity. Our CPU has a configurable architecture and machine language. Yes, you can invent your own assembly instructors to add functionality. We will cover registers, data/address busses, memory‌ (ROM/RAM), IO, and assemblers.��Specs for nerds: 8-bit words, 256 memory addresses, Von Neumann w/ shared address+data bus, DMA with numpy based buffer.��Bio:�Zak Kohler is a Chemical Engineer by education but true computer geek at heart. He started programming in 3rd grade and has never looked back. Often zak states that his biggest regret is not finding Python and Linux sooner...that didn't happen until university. Electronics is his second love and he fuses the two by playing with early computer hardware as well as modern microcontrollers. When zak isn't messing with computers he can be found turning milk into cheese, drawing, or exploring the world on long walks. �

Setup and Play Along

$ git clone https://y2kbugger@bitbucket.org/y2kbugger/SAPy.git�$ cd SAPy

$ pipenv install --dev # *note

$ pipenv shell # Will launch shell (e.g. bash) in venv

(SAPy) $ jupyter notebook

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Python 3.7 !!

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If you don't have pipenv, install it using your package manager as a user pip package:

$ pacman -S python-pipenv # arch linux

$ brew install pipenv # homebrew on osx

$ pip install --user pipenv # pip

$ conda install pipenv # windows/anaconda

zak@zakkohler.com

Learn how computers work between silicon and assembly

Build a CPU with Python

2018-10-29 zak Kohler

Zak Kohler

(y2kbugger)

• Chemical Engineering, University of Akron 2010
• Materials engineer turned software developer

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• Relevant Interests:
• programming, electronics, retrocomputing�
• Irrelevant Interests:
• drawing, punk rock, cheesemaking

Grey Title

Normal text

Blue Text box

Useful Shortcuts/Bash Review

Definition : <Ctrl>

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A Long Text with code below:

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$ pkg install python

$ pip install pip --upgrade

Note on PIP_REQUIRE_VIRTUALENV https://stackoverflow.com/questions/27410821/how-to-prevent-pip-install-without-virtualenv

Intermediate Section

(with a subheading, or aside)

$ vim fun.py

run with <F5> (VolUp + 5)

1 import requests¬

2 req = requests.get("http://cohpy.org")¬

3 print(req.text)¬

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Motivation

Abstraction

Simple interfaces allow complex systems

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You don't think about radios each time you send a text via sms,

this is normally considered a good thing.

Video Series on Computer Science "Up another level of abstraction"

https://www.youtube.com/watch?v=tpIctyqH29Q

Abstractions in Computers

Applications

Operating System

Physical Silicon Layout

Circuit Schematic

Digital Logic

Datapath

Microcode

IO Systems

CPU / Instruction Set Architecture

Firmware

Compiler

In Real Life Silicon

Hardware

Software

Abstractions in

Programming Languages

Image: http://carlcheo.com/compsci

Abstraction in electrical engineering

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Programmers using libraries of code with Application Programming Interfaces (APIs).

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Electrical engineers design using a library of parts with specified electrical interfaces.

Wikipedia: Lumped Element Model

https://en.wikipedia.org/wiki/Lumped_element_model

There was still some magic

Applications

Operating System

Physical Silicon Layout

Circuit Schematic

Digital Logic

Datapath

Microcode

IO Systems

Instruction Set Architecture

Firmware

Compiler

In Real Life Silicon

Hardware

Software

In pursuit of killing the magic I've been playing with hardware recently

This talk is a step towards building a IRL CPU

Outline

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1. Hex & Assembly
2. The SAPy Architecture
3. Clocks, Registers, and Busses
4. Review each CPU component
5. Microprogram Sequencing
6. Connect to software development

Hex/Binary

Hex values 0, 1, ..., E, F are equal to decimal 0, 1, ..., 14, 15

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15 == 0xF == 0b1111

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The maximum value for 1 Byte or 8 bits is

255 == 0xFF == 0b1111_1111

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Hex is also show using $, e.g. 0xFF == $FF

Example of C-like --> Assembly

main()

{

int a=4;

int x=3;

while(1)

{

a += x

putchar(a)

}

}

0x00 LDA $07

0x02 ADD $08

0x04 OTA ; Output a

0x05 JMP $02 ; loop back

0x07 $04 ; a

0x08 $03 ; x

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Assembly Language

Can basically translate directly to machine code

Assembly/machine code is specific to a specific CPU architecture, e.g. x86, ARM, SAPy-16

Allows you to use Mnemonics instead of numbers.

e.g.

LDA #$07 vs 00100000 00000111

Machine Code Execution

0x00 LDA $0A�0x02 ADD $0B�0x04 DMA�0x05 STA $09�0x07 JMP $02

0x09 $00

0x0A $99

0x0B $0E

Our Virtual Machine: based on SAP-1 (Simple As Possible)

Digital Computer Electronics

By: Albert Paul Malvino

The Ben Eater SAP-1

Show Video

Ben Eater "8-bit computer update"

https://www.youtube.com/watch?v=HyznrdDSSGM

SAPy-16 Instructions

Binary: AAAA BBBB [CCCCCCCC]�HEX: AB [CC]

A - Addressing Mode; e.g. Absolute, Immediate�B - Operator; e.g. Load value into A Register�C - Operand, value or address of value; e.g. $D7

* Not all instructions have a operand

�

SAPy-16 Instructions

LDA - Load value into Accumulator

STA - Store Accumulator to Memory�OUT - Output from Memory�ADD - Add to Accumulator

SUB - Subtract from Accumulator��JMP - Jump execution to somewhere else�

DMA - Allow DMA controller to take over bus

HLT - Halt processing�NOP - Do Nothing�OTA - Output Accumulator�

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Clocking Signals

component.data() # Rising Edge, returns data for a clock cycle.

component.clock() # Falling Edge, get passed data from that was fetched on the rising edge of the clock cycle.

Buses & Registers

SAPy Buses & Registers

8

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B

I

T

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B

U

S

8

8

8

Accumulator (Reg A)

□□□□ □□□□

Output Register (Reg O)

□□□□ □□□□

Shared data and address bus

Control bus

Register Transfer

Goal:

Move byte around CPU

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Requirements:

- Exactly one "enable"

- One or more "latching"

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E.g. OTA

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​

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Take how the controls are controlled for granted, for now

8

​

B

I

T

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B

U

S

8

8

8

Accumulator (Reg A)

□□□□ □□□□

Output Register (Reg O)

□□□□ □□□□

Program Counter

The program counter (PC) tracks of where in memory the next instruction to execute is.

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The PC is incremented as each instruction is fetched.

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To execute an instruction other than the next sequential one in memory, you can set the PC to an arbitrary memory address, this allows loops and subroutines.

8

​

B

I

T

​

B

U

S

8

8

Program Counter (PC)

□□□□ □□□□

Accumulator (Register A)

>>> reg_a = RegisterA()

>>> reg_a.data(ea=True)

0

>>> reg_a.clock(data=0xAB, la=True)

>>> reg_a.data(ea=True)

171

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8

​

B

I

T

​

B

U

S

8

8

Accumulator (Reg A)

□□□□ □□□□

Arithmetic Logic Unit

8

​

B

I

T

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B

U

S

8

8

Accumulator (Reg A)

□□□□ □□□□

8

Register B

□□□□ □□□□

8

ALU

□□□□ □□□□

8

8

Memory

Think of ram as a bunch of registers. There is a special circuit that turns an address into an enable for the correct register.

8

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B

I

T

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B

U

S

8

Memory Address Reg (MAR)

□□□□ □□□□

8

RAM 16 x 8 bit

0x00 □□□□ □□□□

0x01 □□□□ □□□□

0x02 □□□□ □□□□

0x03 □□□□ □□□□

...

0xFF □□□□ □□□□

8

MAR

□□□□ □□□□⬜

8

Address Decoder

↑

256 Registers

↓

Controller

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Sequencer

Each instruction takes 6 clock cycles. T-State cycles 1 through 6.

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Decoder

For each combination of opcode and T-state a specific control word is defined

8

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B

I

T

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B

U

S

Instruction Register

□□□□ □□□□

13

Sequencer/Decoder

T: □

8

8

addressmode

Control Word

LA, EA, LM, LR, ER, LI, ..., EO

opcode

Output (Register O)

reg_o = RegisterOutput()

reg_o.clock(data=0xAB, lo=True)�

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8

​

B

I

T

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B

U

S

8

Output Register (Reg O)

□□□□ □□□□

Example Sequencing: LDA $D4

Fetch Cycle, always the same:

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T1: ('ep', 'lm', 'cp')� T2: ('er', 'li')�

...DECODE BASED ON Instruction Register...

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Execution Cycle, based on decoding:

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Absolute addressing:�T3:('ep', 'lm', 'cp')�T4:('er', 'lm')

STA:

T5:('er', 'la')

Memory Mapped vs Port Mapped IO

Operating Systems

First operating system: Human operators

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• Batch Processed
• Each program has full control of the entire mainframe.

Abstracting Hardware

The job of an operating system is to abstract away hardware. They do this by implementing standard interface for tasks that talk to real world.

• Drivers
• Memory allocation
• File systems�

Timesharing

• Interrupts
• Multitasking

Imagine if this guy had to manually set the program counter each time a human interrupted with some input...or change out one job for another thousands of times per second.

Subtleties of Performance

IO vs CPU bottleneck

Quirks of Legacy - Strings

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Try thinking of hardware when you are wondering:

"Why would anyone ever do it like this?"

Security

• jump instructions
• hardware bugs, spektor, etc
• microcode fixes

Let's review the implementation

• Data, clock, component
• Control word
• How to add new opcode

Further Learning

Topics Not Covered

• Pipelining
• Networks
• Memory Protection
• Cache
• SuperScalar execution
• Out of Order execution
• Multithreading
• SIMD
• GPUS

• Physics of Electronics
• Columbus Homebrew

Others

Ben Eater - >40 videos, building on breadboard�Crash Course Computer Science - Very approachable

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Email for endless youtube links on related things:

https://www.youtube.com/watch?v=Gp5KDGqQYP0