DIGITAL SYSTEM DESIGN Using hdl

SIR CRREDDY COLLEGE OF ENGG

Source :

DIGITAL System Design with FPGA implementation using Verilog & VHDL – CemUnsalan, BoraTar McGraw-Hill Education,2017.

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Chapter 5�Introduction to Verilog �

Digital System Design with FPGA: Implementation using Verilog and VHDL

Layout

• Introduction
• Verilog Fundamentals
• Module Representation
• Structural Modeling
• Dataflow Modeling
• Behavioral Modeling
• Timing and Delays in Modeling
• Hierarchical Module Representation
• Testbench Formation in Verilog
• Structure of a Verilog Testbench File
• Displaying Test Results
• Adding an Existing IP to the Project
• Adding an Existing IP in Verilog
• Adding an Existing IP in VHDL

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Digital System Design with FPGA: Implementation using Verilog and VHDL

Introduction

Hardware description languages (HDL) help us formalizing and representing a digital system at hand.

Hence, it can be implemented on a target FPGA platform.

Two popular HDLs are Verilog and VHDL.

We will explore these HDLs in detail in representing digital systems in the following chapters.

Digital System Design with FPGA: Implementation using Verilog and VHDL

Verilog Fundamentals

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A digital system can be represented as a module with the following structure in Verilog.

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Module Representation

• The module should have
• a unique name which should not be the same as any of the predefined Verilog keywords.
• input and output ports assigned to it.
• Internal structure of the module.
• define port elements within the module. Each element can be input, output, or inout.
• describe the digital system.
• close the module by keyword endmodule.
• We can use the symbol // to add a comment to the Verilog description.

Module {module_name} (port_list );

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// Port definitions:

Input,output,inout.

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//Declaration :

Wire,reg,parameters,

Functions,task....

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statement :

Initial statement

always statement

Module instantiations

Gate instantiations

Continuous assignment

...

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

Verilog Fundamentals

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Module Representation : example

Module {module_name} (port_list );

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// Port definitions:

Input,output,inout.

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//Declaration :

Wire,reg,parameters,

Functions,task....

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statement :

Initial statement

always statement

Module instantiations

Gate instantiations

Continuous assignment

...

endmodule

All ports are of size 1-bit since no range is Specified. Also four ports are of NET data type since no declaration has specified.

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Vivado allows adding simulation timings in Verilog descriptions.
• Moreover, if a blank Verilog file is to be opened, Vivado adds the first line automatically as ‘timescale 1ns / 1ps.
• These are the default timing values such that the first one (1ns) indicates the reference time unit.
• Whenever a time value is added to the Verilog description, it will be in the order of one nanosecond.
• The second timing value (1ps) indicates the smallest precision that can be achieved. Hence, the default smallest precision in simulation is one picosecond.
• Ex: assign #2 sum = a ^ b ;
• The #2 refers to 2 time units the association of a time unit with physical time is made using the ‘timescale’ compiler directive
• ex: timescale 1ns / 100ps

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Timing and Delays in Modeling

Verilog Fundamentals

Digital System Design with FPGA: Implementation using Verilog and VHDL

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• In this method, the relation between input and output ports is formed as a function.
• This description method is also called functional modeling.
• The main keyword in dataflow modeling is assign. The syntax here is

assign output = function of inputs.

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• The delay specifies the time duration b/n a change on righ-hand side and the assignment to the left-hand side.
• If no delay value is specified, the default is zero delay
• As in structural modeling, we will only consider logic gates AND, OR, NOT, and XOR here. Corresponding operators to be used in dataflow modeling are & , | , ∼ , ˆ respectively.

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Dataflow Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

9

Dataflow Modeling: Continuous Assignment

A continuous assignment assigns a value to a net

The target in a continuous assignment can be as follows

1. Scalar net
2. Vector net
3. Constant bit-select of a vector
4. Constant part-select of a vector
5. Concatenation of any of the above.

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Dataflow Modeling: Continuous Assignment

Example 1:

Example 2:

Target is a concatenation of a scalar net and vector net

Dataflow Modeling: example 2 : 4 Decoder

Digital System Design with FPGA: Implementation using Verilog and VHDL

12

Dataflow Modeling: example FULL ADDER

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• Each element to be used in the description statement should have been defined under Verilog as a structure.
• Since logic gates are extensively used in Verilog descriptions, they have been defined beforehand.
• This description method is also called as gate-level modeling.
• Each gate is represented by the following structure in this method.
• First, gate type is defined by the corresponding Verilog keyword.
• Then, a name for the gate is assigned.
• Finally, output and input ports for the gate are defined within parenthesis.
• The structural model of a logic gate will be as

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gate_keyword instance_name (port_list).

• The port list should be such that output of the structure is defined first.

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Structural Modeling

Verilog Fundamentals

Digital System Design with FPGA: Implementation using Verilog and VHDL

Structural modeling is described using

• Gate instantiation
• Module instantiation.

Structural Modeling

Module definition

Module instantiation :

Port association can be by Position or By Name instantiation

Digital System Design with FPGA: Implementation using Verilog and VHDL

Where port_expr can be

1. An identifier( register or net)
2. A bit-select
3. A part-select
4. A concatenation of the above
5. An expression(only input ports)

Structural Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Write verilog code for full adder using structural modeling

Structural Modeling

Sol:

• Identify total no of unique components.

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• Write module definition for each component

Digital System Design with FPGA: Implementation using Verilog and VHDL

Write verilog code for full adder using structural modeling

Structural Modeling

1. Module: half adder(hf)

module HF (A,B,S,C);

input A,B;

output Sum, Carry;

assign S = A ^ B;

assign C= A & B;

endmodule

2. Module: or gate(or_2)

module or_2 (X,Y,Z);

input X,Y;

output Z;

assign Z = X & Y;

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

Write verilog code for full adder using structural modeling

Structural Modeling

3 TOP Module: FULL ADDER (FA)

module FA (P,Q,Cin,Sum,Cout);

input P,Q,Cin;

output Sum, Cout;

wire S1,C1,C2;

// two module instantiation:

// associating by position.

Hf h1 (P,Q,S1,C1) ;

// associating by name.

Hf h2 (.A(Cin), .B(S1), .S(Sum), .C(C2)) ;

Or_2 O1(C1,C2,Cout);

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

Write verilog code for full adder using structural modeling

Structural Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Write verilog code for full adder using structural modeling

Structural Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Verilog Fundamentals

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• In this method, digital system is represented by its behavior.
• In other words, Verilog keywords corresponding to conditional and recursive statements can be used within the model.
• In behavioral modeling, statement (or statements) to be executed should be triggered by a signal (or signals) to operate.
• The keyword always is used to indicate this triggering operation.
• Once the signal changes its state, the statement is executed.
• If there is more than one statement to be executed, then they should be encapsulated by begin and end keywords.

Behavioral Modeling:

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Primary mechanism for modeling behavioural of a design has 2 statements
• Initial statements
• Always statements.
• Both the statements executes concurrently starting at time 0 units.
• An initial statement executes only once it begins its execution at start of simulation which is at time 0.
• The syntax for initial statement is

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• where a procedural_statement is one of

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Behavioral Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

• where a procedural_statement is one of

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Behavioral Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Syntax for this representation becomes

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always @ (sensitivity_list)

begin

// behavioral description

statement 1

statement 2

statement 3

...

end

Behavioral Modeling

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• The sensitivity list stands for triggering signal(s).
• The sensitivity list can be formed of signals separated by comma or combined by or keyword.
• If the behavioral description is to be executed for any input changes, then * sign can be used instead of the sensitivity list.
• Whenever one of the signals in the sensitivity list changes its state, the behavioral description is executed.

The syntax for always statement is

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Procedural assignment statements
• Procedural assignments are employed for updating the memory variables. These assignments control the flow and keep updating the new data to the variables in the left-hand side expression on the activation of the sensitivity list.
• It represents a logical statement in hardware design. It just represents the boolean logic or the algebraic expression of the circuit. These appear only under the always block.
• There are two kinds of procedural assignment statements:
• Blocking statements
• Non-blocking statements
• The main reason to use either Blocking or Non-blocking assignments is to generate either combinational or sequential logic

Behavioral Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Blocking statements 

• Blocking assignments are executed in the order they are coded. Hence, they are conbinational. Since they block the execution of the next statement, until the current statement is executed, they are called blocking assignments.
• The assignment is made with the “=” symbol.

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Behavioral Modeling

// Blocking Assignment

Initial

begin

// here, the begin-end clause is used because there are more than one statements in the initial block

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#10 a = 0; // 10 time units delay has been given a with value 0

#11 a = 1; // 11 time units delay to a variable with value 1

#12 a = 0; // 12 time units delay to a with value 0

#13 a = 1; // 13 time units delay to a with value 1

end

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Non-blocking statements
• Non-blocking assignments are executed in parallel. Hence, they are sequential. Since the execution of the next statement is not blocked due to the execution of the current statement, they are called non-blocking statements.
• Assignments are made with the “<=” symbol.

Behavioral Modeling

// Non-blocking Assignment

initial

begin

// These statements will get executed without the intervention of the other statements

// In other words, their execution will not be blocked by the other ones

#10 b <= 0; // A delay of 10 time units has been given to the variable b with 0 value.

#11 b <= 1; // 11 time units delay to b with value 1

#12 b <= 0; // 12 time units delay to b with value 0

#13 b <= 1; // 13 time units delay to b with value 1

end

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Example fulladder using half adder using behavioral modelling.

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There are different ways we can proceed with Verilog coding for full adder:

• Using an always statement
• Case statements
• If-else statements

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Behavioral Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

Using always statement:

• This is the most general way of coding in behavioral style. What we do over here is; select the sensitivity list first, the change in which your output depends in almost every case, the input ports comprise the sensitivity list.

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Behavioral Modeling

// Procedural statements inside this always block gets executed once there’s any change in event A, B OR Cin. 

`timescale 1ns / 1ps

module full_adder( A, B, Cin, S, Cout);

input A, B, Cin;

Output S, Cout;

always @(A or B or Cin) // or keyword is not performing logical-or

begin

S = A ^ B ^ Cin;

Cout = A&B | (A^B) & Cin;

end

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

Using case statement :

• The case statement in Verilog is much similar to switch- case statement in C language. It is one of the procedural statements in Verilog.
• The expressions are executed once it fulfills the case_expression to its case_item value. If the case_expression doesn’t meet any of the case_item values, the default option is chosen at last.
• The case_expression is evaluated first. Next, the case_item expressions are evaluated and compared in the given order. The set of statements that match the first true condition is executed.

Behavioral Modeling

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case (case_expression)   

    case_item1: procedural_expression;

   case_item2: begin procedural_statements;          

end            ....    default: expression;

endcase

Digital System Design with FPGA: Implementation using Verilog and VHDL

Behavioral Modeling

`timescale 1ns / 1ps

module full_adder( A, B, Cin, S, Cout);

input A, B, Cin;

Output S, Cout;

always @(A or B or Cin) // or keyword is not performing logical-or

begin

case (A | B | Cin)

3'b000: begin S = 0; Cout = 0; end

3'b001: begin S = 1; Cout = 0; end

3'b010: begin S = 1; Cout = 0; end

3'b011: begin S = 0; Cout = 1; end

3'b100: begin S = 1; Cout = 0; end

3'b101: begin S = 0; Cout = 1; end

3'b110: begin S = 0; Cout = 1; end

3'b111: begin S = 1; Cout = 1; end

endcase

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

Using if-else statement:

• if condition_1 evaluates to a non- zero value, then the procedural_statement_1 is executed. If condition_2 evaluates to a value 0, X or Z, the procedural_statement_1 will not be executed, and an else branch, if it exists, is executed.

Behavioral Modeling

if(condition_1)

procedural_statement_1;

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else if(condition_2)  

procedural_statement_2;

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else procedural_statement_3;

Digital System Design with FPGA: Implementation using Verilog and VHDL

Behavioral Modeling

`timescale 1ns / 1ps

module full_adder( A, B, Cin, S, Cout);

input A, B, Cin;

Output S, Cout;

always @(A or B or Cin) // or keyword is not performing logical-or

Begin

if(A==0 && B==0 && Cin==0)

begin

S=0; Cout=0;

end

else if(A==0 && B==0 && Cin==1)

begin

S=1; Cout=0;

end

else if(A==0 && B==1 && Cin==0)

begin

S=1; Cout=0;

end

else if(A==0 && B==1 && Cin==1)

begin

S=0; Cout=1;

end

else if(A==1 && B==0 && Cin==0)

begin

S=1; Cout=0;

end

else if(A==1 && B==0 && Cin==1)

begin

S=0; Cout=1;

end

else if(A==1 && B==1 && Cin==0)

begin

S=0; Cout=1;

end

else if(A==1 && B==1 && Cin==1)

begin

S=1; Cout=1;

end

end

endmodule

Digital System Design with FPGA: Implementation using Verilog and VHDL

One other important Verilog keyword for behavioral modeling is initial. this keyword, an initial block can be formed which is executed at time zero. Syntax of the initial block is

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initial

begin

statements

end

Behavioral Modeling

Digital System Design with FPGA: Implementation using Verilog and VHDL

• In larger projects, the number of modules may be more than one.
• A project with more than one module can also be constructed.

Hierarchical Module Representation

Each module represented as a black box

Each module represented as it is

Digital System Design with FPGA: Implementation using Verilog and VHDL

Hierarchical Module Representation

Each module represented as a black box

Each module represented as it is

Digital System Design with FPGA: Implementation using Verilog and VHDL

Testbench Formation in Verilog

Characteristics of a digital system can be analyzed in Vivado by using a testbench.

A Verilog testbench file is composed of five parts as follows.

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• Testbench module declaration.
• Input/output port declaration.
• Instantiation of the unit under test (UUT).
• Providing input to the UUT.
• Displaying test results.

Structure of a Verilog Testbench File

Digital System Design with FPGA: Implementation using Verilog and VHDL

1.Testbench module declaration.

• The testbench is itself a Verilog module. Therefore, it needs valid module and input/output port declarations. This is the first step in testbench formation.
• These declarations are done as follows

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Testbench Formation in Verilog

• First the simulation timing value is declared by the timescale keyword. Then, the testbench module is declared as module first_system_tb.
• We specifically assigned such a name to the testbench module to associate it with the top module to be tested.
• Next, input and output ports of the test-bench module are declared as reg in1t, in2t and wire out1t, out2t.
• The reader is free to choose any valid name here.

Digital System Design with FPGA: Implementation using Verilog and VHDL

Verilog Description of the First System-the Top Module

Testbench Formation in Verilog

2.Input/output port declaration

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Digital System Design with FPGA: Implementation using Verilog and VHDL

Verilog Description of the First System–the Supplement File

Testbench Formation in Verilog

2.Input/output port declaration

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Digital System Design with FPGA: Implementation using Verilog and VHDL

• The next step in testbench formation is associating the module to be tested (Unit Under Test) with the testbench module.

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• Hierarchical module declaration, the module to be tested (for our case first_ system) is instantiated in the testbench module with the name UUT.
• Then, each port in the testbench module and the module to be tested are associated (or connected) such as .out1(out1t).
• Here, the port in the module to be tested is declared as .out1.
• The corresponding port in the testbench module is declared as (out1t). This operation is done for all input/output ports.

Testbench Formation in Verilog

3.Instantiation of the unit under test (UUT)

Digital System Design with FPGA: Implementation using Verilog and VHDL

• The next step in testbench formation is providing input to the UUT.

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Testbench Formation in Verilog

4. Providing input to the UUT.

• Testbench input ports (in1t and in2t) are initialized first. Then, a delay of 100 ns is added by the command #100.
• This delay is added such that the module to be tested is reset properly

Digital System Design with FPGA: Implementation using Verilog and VHDL

• Next, input values are fed to the UUT. This is done in two lines as follows.
• The first line contains the command repeat (4). This indicates that the following line will be repeated four times.
• The second line contains the command

#100 { in1t, in2t } = {in1t, in2t } + 1’b1.

• This indicates that inputs will be incremented one by one sweeping the pattern 00, 01, 10, and 11.
• Transition between each input combination is done after a 100-ns delay

Testbench Formation in Verilog

4. Providing input to the UUT.

Digital System Design with FPGA: Implementation using Verilog and VHDL

There are two options to observe simulation results in Vivado.

• The first one is through input/output waveforms.
• The second option in observing output of the test is adding specific display
• commands such that output can be observed through Vivado’s Tcl console.

5.Displaying Test Results

Digital System Design with FPGA: Implementation using Verilog and VHDL