Register Transfer and Micro operations

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Chapter No - 4

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contents

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• Register Transfer Language

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• Register Transfer

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• Bus and Memory Transfers

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• Arithmetic Microoperations

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• Logic Microoperations

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• Shift Microoperations

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• Arithmetic Logic Shift Unit

4-1 Register Transfer Language (RTL)

• Digital System: An interconnection of hardware modules that do a certain task on the information.
• Registers + Operations performed on the data stored in them = Digital Module
• Modules are interconnected with common data and control paths to form a digital computer system

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4-1 Register Transfer Language cont.

• Microoperations: operations executed on data stored in one or more registers.
• For any function of the computer, a sequence of

microoperations is used to describe it

• The result of the operation may be:
• replace the previous binary information of a register or
• transferred to another register

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101101110011

010110111001

Shift Right Operation

4-1 Register Transfer Language ^cont.

• The internal hardware organization of a digital computer is defined by specifying:
• The set of registers it contains and their function
• The sequence of microoperations performed on the binary information stored in the registers
• The control that initiates the sequence of microoperations
• Registers + Microoperations Hardware + Control Functions = Digital Computer

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4-1 Register Transfer Language ^cont.

• Register Transfer Language (RTL) : a symbolic notation to describe the microoperation transfers among registers

Next steps:

• Define symbols for various types of microoperations,
• Describe the hardware that implements these microoperations

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4-2 Register Transfer (our first microoperation)

• Computer registers are designated by capital letters (sometimes followed by numerals) to denote the function of the register
• R1: processor register
• MAR: Memory Address Register (holds an address for a memory unit)
• PC: Program Counter
• IR: Instruction Register
• SR: Status Register

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4-2 Register Transfer ^cont.

• The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 (from the right position toward the left position)

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R1

7 6 5 4 3 2 1 0

A block diagram of a register

Register R1

Showing individual bits

4-2 Register Transfer ^cont.

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PC

Numbering of bits

Partitioned into two parts

15

0

PC(H)

PC(L)

0

7

8

15

Lower byte

Upper byte

Other ways of drawing the block diagram of a register:

4-2 Register Transfer ^cont.

• Information transfer from one register to another is described by a replacement operator: R2 ← R1
• This statement denotes a transfer of the content of register R1 into register R2
• The transfer happens in one clock cycle
• The content of the R1 (source) does not change
• The content of the R2 (destination) will be lost and replaced by the new data transferred from R1
• We are assuming that the circuits are available from the outputs of the source register to the inputs of the destination register, and that the destination register has a parallel load capability

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4-2 Register Transfer ^cont.

• Conditional transfer occurs only under a control condition

​

• Representation of a (conditional) transfer

P: R2 ← R1

• A binary condition (P equals to 0 or 1) determines when the transfer occurs
• The content of R1 is transferred into R2 only if P is 1

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4-2 Register Transfer ^cont.

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n

Clock

R1

R2

Control Circuit

Load

t

t+1

Clock

Load

Transfer occurs here

Synchronized with the clock

P

Hardware implementation of a controlled transfer: P: R2 ← R1

Block diagram:

Timing diagram

4-2 Register Transfer ^cont.

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4-3 Bus and Memory Transfers

• Paths must be provided to transfer information from one register to another
• A Common Bus System is a scheme for transferring information between registers in a multiple-register configuration
• A bus: set of common lines, one for each bit of a register, through which binary information is transferred one at a time
• Control signals determine which register is selected by the bus during each particular register transfer

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4-3 Bus and Memory Transfers

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3 2 1 0

Register D

D₃ D₂ D₁ D₀

3 2 1 0

Register C

C₃ C₂ C₁ C₀

3 2 1 0

Register B

B₃ B₂ B₁ B₀

3 2 1 0

Register A

A₃ A₂ A₁ A₀

D₃ C₃ B₃ A₃

S₀

S₁

MUX3

3 2 1 0

D₂ C₂ B₂ A₂

S₀

S₁

MUX2

3 2 1 0

D₁ C₁ B₁ A₁

S₀

S₁

MUX1

3 2 1 0

D₀ C₀ B₀ A₀

S₀

S₁

MUX0

3 2 1 0

4-Line Common Bus

4-3 Bus and Memory Transfers

• The transfer of information from a bus into one of many destination registers is done:
• By connecting the bus lines to the inputs of all destination registers and then:
• activating the load control of the particular destination register selected
• We write: R2 ← C to symbolize that the content of register C is loaded into the register R2 using the common system bus
• It is equivalent to: BUS ←C, (select C)

R2 ←BUS (Load R2)

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4-3 Bus and Memory Transfers: Three-State Bus Buffers

• A bus system can be constructed with three-state buffer gates instead of multiplexers
• A three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and high-impedance (Hi-Z)

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Normal input A

Control input C

Three-State Buffer

Output B

4-3 Bus and Memory Transfers: Three-State Bus Buffers ^cont.

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A

C=1

B

A

B

A

C=0

B

A

B

Buffer

Open Circuit

4-3 Bus and Memory Transfers: Three-State Bus Buffers ^cont.

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2×4 Decoder

Select

Enable

0

1

2

3

S₁

S₀

E

Bus line for bit 0

A₀

B₀

C₀

D₀

Bus line with three-state buffer (replaces MUX0 in the previous diagram)

4-3 Bus and Memory Transfers: Memory Transfer

• Memory read : Transfer from memory
• Memory write : Transfer to memory
• Data being read or wrote is called a memory word (called M)- (refer to section 2-7)
• It is necessary to specify the address of M when writing /reading memory
• This is done by enclosing the address in square brackets following the letter M
• Example: M[0016] : the memory contents at address 0x0016

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4-3 Bus and Memory Transfers: Memory Transfer ^cont.

• Assume that the address of a memory unit is stored in a register called the Address Register AR
• Lets represent a Data Register with DR, then:
• Read: DR ← M[AR]
• Write: M[AR] ← DR

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4-3 Bus and Memory Transfers: Memory Transfer ^cont.

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AR

x12

x0C

x0E

x10

x12

x14

x16

x18

19

34

45

66

0

13

22

R1←M[AR]

R1

100

R1

66

RAM

R1

100

4-4 Arithmetic Microoperations

• The microoperations most often encountered in digital computers are classified into four categories:
• Register transfer microoperations
• Arithmetic microoperations (on numeric data stored in the registers)
• Logic microoperations (bit manipulations on non-numeric data)
• Shift microoperations

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4-4 Arithmetic Microoperations ^cont.

• The basic arithmetic microoperations are: addition, subtraction, increment, decrement, and shift
• Addition Microoperation:

R3 ←R1+R2

• Subtraction Microoperation:

R3 ←R1-R2 or :

R3 ←R1+R2+1

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1’s complement

4-4 Arithmetic Microoperations ^cont.

• One’s Complement Microoperation:

R2 ←R2

• Two’s Complement Microoperation:

R2 ←R2+1

• Increment Microoperation:

R2 ←R2+1

• Decrement Microoperation:

R2 ←R2-1

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Half Adder/Full Adder

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Half Adder

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

c_n = xy + xc_n-1+ yc_n-1

= xy + (x ⊕ y)c_n-1

​

s = x’y’c_n-1+x’yc’_n-1+xy’c’_n-1+xyc_n-1

= x ⊕ y ⊕ c_n-1 = (x ⊕ y) ⊕ c_n-1

x

y

c_n-1

x

y

c_n-1

c_n

s

c = xy s = xy’ + x’y

= x ⊕ y

x

y

c_n-1

S

​

​

c_n

Full Adder

x y c_n-1 c_n s

0

0

1

0

0

1

1

1

0

1

0

1

1

0

1

0

4-4 Arithmetic Microoperations Binary Adder

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C₀

A₀

B₀

S₀

A₁

B₁

S₁

A₂

B₂

S₂

A₃

B₃

S₃

C₁

C₂

C₃

C₄

4-bit binary adder (connection of FAs)

4-4 Arithmetic Microoperations Binary Adder-Subtractor

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C₀

A₀

B₀

S₀

A₁

B₁

S₁

A₂

B₂

S₂

A₃

B₃

S₃

C₁

C₂

C₃

C₄

4-bit adder-subtractor

M

4-4 Arithmetic Microoperations Binary Adder-Subtractor

• For unsigned numbers, this gives A – B if A≥B or the 2’s complement of (B – A) if A < B

(example: 3 – 5 = -2= 1110)

• For signed numbers, the result is A – B provided that there is no overflow. (example : -3 – 5= -8) 1101

1011 +

ـــــــــــــــــــــــــــ

1000

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C₃

C₄

V =

1, if overflow

0, if no overflow

Overflow detector for signed numbers

4-4 Arithmetic Microoperations Binary Adder-Subtractor ^cont.

• What is the range of unsigned numbers that can be represented in 4 bits?
• What is the range of signed numbers that can be represented in 4 bits?
• Repeat for n-bit?!

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4-4 Arithmetic Microoperations Binary Incrementer

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C

S

x

y

HA

C

S

x

y

HA

C

S

x

y

HA

C

S

x

y

HA

S₀

S₁

S₂

S₃

C₄

1

A₀

A₁

A₂

A₃

4-bit Binary Incrementer

4-4 Arithmetic Microoperations Binary Incrementer

• Binary Incrementer can also be implemented using a counter
• A binary decrementer can be implemented by adding 1111 to the desired register each time!

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4-4 Arithmetic Microoperations Arithmetic Circuit

• This circuit performs seven distinct arithmetic operations and the basic component of it is the parallel adder
• The output of the binary adder is calculated from the following arithmetic sum:
• D = A + Y + C_in

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4-4 Arithmetic Microoperations Arithmetic Circuit ^cont.

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B₀

3 2 1 0 S₁ S₀

4×1 MUX

FA

FA

FA

FA

C_in

D₀

D₁

D₂

D₃

C₁

C₂

C₃

C_out

B₀

1

0

S₁

S₀

B₁

3 2 1 0 S₁ S₀

4×1 MUX

B₁

1

0

S₁

S₀

B₂

3 2 1 0 S₁ S₀

4×1 MUX

B₂

1

0

S₁

S₀

B₃

3 2 1 0 S₁ S₀

4×1 MUX

B₃

1

0

S₁

S₀

A₀

A₁

A₂

A₃

4-bit Arithmetic Circuit

X₀

Y₀

X₁

Y₁

X₂

Y₂

X₃

Y₃

Figure A

4-5 Logic Microoperations�The four basic microoperations

OR Microoperation

• Symbol: ∨, +

​

• Gate:

​

• Example: 100110₂ ∨ 1010110₂ = 1110110₂

​

P+Q: R1←R2+R3, R4←R5 ∨R6

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OR

OR

ADD

4-5 Logic Microoperations�The four basic microoperations ^cont.

AND Microoperation

• Symbol: ∧

​

• Gate:

​

• Example: 100110₂ ∧ 1010110₂ = 0000110₂

​

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4-5 Logic Microoperations�The four basic microoperations ^cont.

Complement (NOT) Microoperation

• Symbol: ⁻

​

• Gate:

​

• Example: 1010110₂ = 0101001₂

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4-5 Logic Microoperations�The four basic microoperations ^cont.

XOR (Exclusive-OR) Microoperation

• Symbol: ⊕

​

• Gate:

​

• Example: 100110₂ ⊕ 1010110₂ = 1110000₂

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4-5 Logic Microoperations�Other Logic Microoperations

Selective-set Operation

• Used to force selected bits of a register into logic-1 by using the OR operation

• Example: 0100₂ ∨ 1000₂ = 1100₂

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In a processor register

Loaded into a register from memory to perform the selective-set operation

4-5 Logic Microoperations�Other Logic Microoperations ^cont.

Selective-complement (toggling) Operation

• Used to force selected bits of a register to be complemented by using the XOR operation

• Example: 0001₂ ⊕ 1000₂ = 1001₂

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In a processor register

Loaded into a register from memory to perform the selective-complement operation

4-5 Logic Microoperations�Other Logic Microoperations ^cont.

Insert Operation

• Step1: mask the desired bits
• Step2: OR them with the desired value

• Example: suppose R1 = 0110 1010, and we desire to replace the leftmost 4 bits (0110) with 1001 then:
• Step1: 0110 1010 ∧ 0000 1111
• Step2: 0000 1010 ∨ 1001 0000
• 🡪 R1 = 1001 1010

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4-5 Logic Microoperations� Other Logic Microoperations ^cont.

NAND Microoperation

• Symbols: ∧ and ⁻

​

• Gate:

​

• Example: 100110₂ ∧ 1010110₂ = 1111001₂

​

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4-5 Logic Microoperations� Other Logic Microoperations ^cont.

NOR Microoperation

• Symbols: ∨ and ⁻

​

• Gate:

​

• Example: 100110₂ ∨ 1010110₂ = 0001001₂

​

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4-5 Logic Microoperations� Other Logic Microoperations ^cont.

Set (Preset) Microoperation

• Force all bits into 1’s by ORing them with a value in which all its bits are being assigned to logic-1
• Example: 100110₂ ∨ 111111₂ = 111111₂

Clear (Reset) Microoperation

• Force all bits into 0’s by ANDing them with a value in which all its bits are being assigned to logic-0
• Example: 100110₂ ∧ 000000₂ = 000000₂

​

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4-5 Logic Microoperations�Hardware Implementation

• The hardware implementation of logic microoperations requires that logic gates be inserted for each bit or pair of bits in the registers to perform the required logic function
• Most computers use only four (AND, OR, XOR, and NOT) from which all others can be derived.

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4-5 Logic Microoperations�Hardware Implementation ^cont.

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S₁

S₀

0

1

2

3

4×1 MUX

E_i

A_i

B_i

This is for one bit i

Figure B

4-6 Shift Microoperations

• Used for serial transfer of data
• Also used in conjunction with arithmetic, logic, and other data-processing operations
• The contents of the register can be shifted to the left or to the right
• As being shifted, the first flip-flop receives its binary information from the serial input
• Three types of shift: Logical, Circular, and Arithmetic

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4-6 Shift Microoperations ^cont.

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r₀

r₁

r₃

r_n-1

r₀

r₁

r₂

r₃

r_n-1

Shift Right

Shift Left

Serial Input

Serial Output

Serial Output

Serial Input

Determines the “shift” type

r2

**Note that the bit ri is the bit at position (i) of the register

4-6 Shift Microoperations: �Logical Shifts

• Transfers 0 through the serial input
• Logical Shift Right: R1←shr R1

​

• Logical Shift Left: R2←shl R2

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The same

The same

Logical Shift Left

?

0

r₀

r₁

r₂

r₃

r_n-1

4-6 Shift Microoperations: �Circular Shifts (Rotate Operation)

• Circulates the bits of the register around the two ends without loss of information
• Circular Shift Right: R1←cir R1

​

• Circular Shift Left: R2←cil R2

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The same

The same

Circular Shift Left

r₀

r₁

r₂

r₃

r_n-1

4-6 Shift Microoperations� Arithmetic Shifts

• Shifts a signed binary number to the left or right
• An arithmetic shift-left multiplies a signed binary number by 2: ashl (00100): 01000
• An arithmetic shift-right divides the number by 2

ashr (00100) : 00010

• An overflow may occur in arithmetic shift-left, and occurs when the sign bit is changed (sign reversal)

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4-6 Shift Microoperations� Arithmetic Shifts ^cont.

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Arithmetic Shift Right

Sign Bit

Arithmetic Shift Left

Sign Bit

?

0

?

r₀

r₁

r₂

r₃

r_n-1

r₀

r₁

r₂

r₃

r_n-1

4-6 Shift Microoperations� Arithmetic Shifts ^cont.

• An overflow flip-flop V_s can be used to detect an arithmetic shift-left overflow

​

V_s = R_n-1 ⊕ R_n-2

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R_n-2

V_s=

R_n-1

1 🡪 overflow

0 🡪 no overflow

4-6 Shift Microoperations ^cont.

• Example: Assume R1=11001110, then:
• Arithmetic shift right once : R1 = 11100111
• Arithmetic shift right twice : R1 = 11110011
• Arithmetic shift left once : R1 = 10011100
• Arithmetic shift left twice : R1 = 00111000
• Logical shift right once : R1 = 01100111
• Logical shift left once : R1 = 10011100
• Circular shift right once : R1 = 01100111
• Circular shift left once : R1 = 10011101

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4-6 Shift Microoperations �Hardware Implementation ^cont.

• A possible choice for a shift unit would be a bidirectional shift register with parallel load (refer to Fig 2-9). Has drawbacks:
• Needs two pulses (the clock and the shift signal pulse)
• Not efficient in a processor unit where multiple number of registers share a common bus
• It is more efficient to implement the shift operation with a combinational circuit

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4-6 Shift Microoperations �Hardware Implementation ^cont.

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S

1

0

S

1

0

S

1

0

S

1

0

A₃

A₂

A₁

A₀

Serial Input I_R

Serial Input I_L

Select

0 for shift right

1 for shift left

H₃

H₂

H₁

H₀

MUX

MUX

MUX

MUX

4-bit Combinational Circuit Shifter

4-6 Shift Microoperations �Hardware Implementation ^cont.

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S

1

0

S

1

0

S

1

0

S

1

0

A₃

A₂

A₁

A₀

Serial Input I_R

Serial Input I_L

Select

0 for shift right

1 for shift left

H₃

H₂

H₁

H₀

MUX

MUX

MUX

MUX

4-bit Combinational Circuit Shifter

4-7 Arithmetic Logic Shift Unit

• Instead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU)

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4-7 Arithmetic Logic Shift Unit ^cont.

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0

1

2

3

S₃

S₂

S₁

S₀

B_i

A_i

A_i+1

A_i-1

Select

4×1 MUX

C_i

C_i+1

One stage of arithmetic circuit (Fig.A)

One stage of logic circuit (Fig.B)

D_i

E_i

F_i

shr

shl

One stage of ALU

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