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CS61C: Great Ideas in Computer Architecture (aka Machine Structures)

Lecture 15: Single-Cycle Datapath II

Instructor: Ariana Abel

Slides Credit: Justin Yokota

CS 61C

Summer 2025

2 of 58

Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

2

CS 61C

Summer 2025

3 of 58

Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

3

CS 61C

Summer 2025

4 of 58

Datapath so far: R, I, S, J types

4

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

CS 61C

Summer 2025

5 of 58

Implementing branch instructions

  • Let's add beq
  • beq compares rs1 and rs2:
    • Need new component for comparisons
  • Then computes one thing:
    • New PC if branch = PC+offset
      • This uses the ALU, so can't use ALU for comparisons - need new block!
  • Then sets one state element:
    • PC+4 if branch not taken, PC+offset if branch is taken
    • Can use PCSel
  • Main issues:
    • Control logic (PCSel) needs to be conditioned on Branch result
    • New immediate type
    • New Branch Comparator

5

CS 61C

Summer 2025

6 of 58

Datapath so far

6

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

CS 61C

Summer 2025

7 of 58

Datapath running beq x5 x6 16

7

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

0x00628863

16

5

6

16

16

PC Sel?

ADD

1

Read

*

0

1

B

*

16

0

CS 61C

Summer 2025

8 of 58

The Branch Comparator

The Branch Comparator will handle all our branch instructions:

Input:

  • Two data busses A and B (corresponding to rs1 and rs2)
  • BrUn control bit: Do unsigned comparison?
    • Only affects BrLt, since == is the same regardless of signed vs unsigned

Output:

  • Two bits:
    • BrEq that's 1 if A==B
    • BrLt that's 1 if A < B
    • Note: A>=B is the same as !(A<B), so no need for BrGe
  • Can decide PCSel based on these outputs, so send to Control Logic

8

Eq

Branch Comp

32

32

BrUn

Lt

CS 61C

Summer 2025

9 of 58

Datapath running beq x5 x6 16 (equality holds)

9

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

0x00628863

16

5

6

Branch Comp

16

16

3

3

PC Sel

ADD

1

Read

*

0

1

B

*

PCSel depends on the result of Branch Comparator; either the pink or the orange path gets used, though both get computed

16

0

CS 61C

Summer 2025

10 of 58

Datapath running beq x5 x6 16 (equality does not hold)

​

10

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

0x00628863

16

5

6

Branch Comp

16

16

3

2

PC Sel

ADD

1

Read

*

0

1

*

RegWEn and MEMRW need to disable writes, since we don't want to change anything except PC.

0

4

B

CS 61C

Summer 2025

11 of 58

Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

11

CS 61C

Summer 2025

12 of 58

Implementing lui

  • Let's add lui
  • lui computes a new immediate type
  • And affects two state elements:
    • rd = imm
    • PC = PC+4

12

CS 61C

Summer 2025

13 of 58

Implementing auipc

  • auipc does the same thing as lui, but it also adds PC to the immediate value

13

CS 61C

Summer 2025

14 of 58

Datapath So Far

14

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

CS 61C

Summer 2025

15 of 58

Datapath running lui x5 0x12345

15

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

0

B

*

Read

1

1

1

U

*

lui doesn't need many changes! All we need is a new ImmGen format and a new ALU operation: return value of B.

5

0x1234 5000

0x1234 5000

0x123452B7

CS 61C

Summer 2025

16 of 58

Datapath running auipc x5 0x12345

16

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

0

ADD

1

Read

1

1

1

U

*

auipc also gets implemented with no changes, by using the PC input we set for jal instructions!

5

0x1234 5000

0x1234 5000

0x12345297

CS 61C

Summer 2025

17 of 58

Complete RISC-V Datapath!!!

17

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

CS 61C

Summer 2025

18 of 58

Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

18

CS 61C

Summer 2025

19 of 58

What's Left?

With the datapath we have, we've reduced the problem of making a CPU to a few small subcircuits:

  • Multiplexers: Discussed in previous lecture, and part of Lab 5
  • ALU/Regfile: Implemented as part of Project 3A
  • Branch Comparator: Implemented as part of Project 3B
  • IMEM/DMEM: Exact implementation out of scope
  • Control Logic: The big one
    • Later in lecture
  • ImmGen: Let's finish this off right now
    • At the same time, we'll notice some clever patterns in how the bits are stored across instruction formats

19

CS 61C

Summer 2025

20 of 58

How to make the ImmGen

Option 1:

  • Make a circuit for each instruction format, then mux the results with ImmSel
  • Ugly, but it works

Option 2:

  • Look for patterns in the instruction format
  • Takes time, but gives much greater insight into why instruction formats were designed this way

20

CS 61C

Summer 2025

21 of 58

Instruction Formats

21

CS 61C

Summer 2025

22 of 58

Tracking all Immediate Bits in each format

22

I

11

10

9

8

7

6

5

4

3

2

1

0

​

​

​

​

​

​

​

​

​

​

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​

​

​

​

​

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​

​

S

11

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

0

​

​

​

​

​

​

​

B

12

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

11

​

​

​

​

​

​

​

U

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

​

​

​

​

​

​

​

​

​

​

​

​

J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

​

​

​

​

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Imm

31

30

29

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27

26

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24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CS 61C

Summer 2025

23 of 58

Tracking all Immediate Bits in each format

23

I

11

10

9

8

7

6

5

4

3

2

1

0

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

​

S

11

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

0

​

​

​

​

​

​

​

B

12

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

11

​

​

​

​

​

​

​

U

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

​

​

​

​

​

​

​

​

​

​

​

​

J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

​

​

​

​

​

​

​

​

​

​

​

Imm

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit 0 of imm: Bit 20 of inst if I type, Bit 7 of inst if S type, always 0 if B/U/J type

CS 61C

Summer 2025

24 of 58

Tracking all Immediate Bits in each format

24

I

11

10

9

8

7

6

5

4

3

2

1

0

​

​

​

​

​

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S

11

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

0

​

​

​

​

​

​

​

B

12

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

11

​

​

​

​

​

​

​

U

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

​

​

​

​

​

​

​

​

​

​

​

​

J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

​

​

​

​

​

​

​

​

​

​

​

Imm

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bits 4-1 of imm: Bits 24-21 of inst if I/J type, Bits 11-8 of inst if S/B type, always 0 if U type. Only found in two parts of the instruction, and these 4 bits are always together.

CS 61C

Summer 2025

25 of 58

Tracking all Immediate Bits in each format

25

I

11

10

9

8

7

6

5

4

3

2

1

0

​

​

​

​

​

​

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S

11

10

9

8

7

6

5

​

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​

​

​

​

​

​

​

​

​

4

3

2

1

0

​

​

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B

12

10

9

8

7

6

5

​

​

​

​

​

​

​

​

​

​

​

​

​

4

3

2

1

11

​

​

​

​

​

​

​

U

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

​

​

​

​

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​

​

​

​

​

​

​

J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

​

​

​

​

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Imm

31

30

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11

10

9

8

7

6

5

4

3

2

1

0

Bits 10-5 of imm: Bits 30-25 of inst if I/S/B/J type, always 0 if U type. Only found in one part of the instruction, even though 4 different instruction formats use it!

CS 61C

Summer 2025

26 of 58

Tracking all Immediate Bits in each format

26

I

11

10

9

8

7

6

5

4

3

2

1

0

​

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S

11

10

9

8

7

6

5

​

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​

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​

​

​

​

​

4

3

2

1

0

​

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B

12

10

9

8

7

6

5

​

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4

3

2

1

11

​

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​

U

31

30

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28

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20

19

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16

15

14

13

12

​

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J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

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Imm

31

30

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5

4

3

2

1

0

MSB of instruction is ALWAYS the MSB of the immediate. Sign-extending is just copying the MSB, and almost all RISC-V immediates sign-extend. To sign-extend, we just take the MSB of the instruction.

CS 61C

Summer 2025

27 of 58

Tracking all Immediate Bits in each format

27

I

11

10

9

8

7

6

5

4

3

2

1

0

​

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S

11

10

9

8

7

6

5

​

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​

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​

​

​

​

​

4

3

2

1

0

​

​

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B

12

10

9

8

7

6

5

​

​

​

​

​

​

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​

​

​

​

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4

3

2

1

11

​

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​

​

​

U

31

30

29

28

27

26

25

24

23

22

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20

19

18

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16

15

14

13

12

​

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J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

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​

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Imm

31

30

29

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25

24

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21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bits 31-21 and 19-12 of immediate: Always the corresponding bit in the instruction if part of the format, and bit 31 otherwise. Only two options for these bits as well

CS 61C

Summer 2025

28 of 58

Tracking all Immediate Bits in each format

28

I

11

10

9

8

7

6

5

4

3

2

1

0

​

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​

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S

11

10

9

8

7

6

5

​

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​

​

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​

4

3

2

1

0

​

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B

12

10

9

8

7

6

5

​

​

​

​

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​

​

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4

3

2

1

11

​

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U

31

30

29

28

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24

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20

19

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15

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12

​

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J

20

10

9

8

7

6

5

4

3

2

1

11

19

18

17

16

15

14

13

12

​

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Imm

31

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11

10

9

8

7

6

5

4

3

2

1

0

Bits 20 and 11 of immediate: Kind of put in random spots where there's space. Bit 20 needs a 2-way mux, and bit 11 needs a 4-way mux

CS 61C

Summer 2025

29 of 58

How to make the ImmGen

Because of how all instruction formats were chosen, there are a lot of underlying patterns in how immediates are stored.

By looking for these patterns, the ImmGen can be greatly simplified (in terms of total number of logic gates)

  • 6-select 32-bit mux = 640 logic gates (counting 2-input OR and ANDs, and 1-input NOTs)
  • Using just muxes for each set of bits, you can get this down to 160 logic gates (best Justin got)
    • Con: Makes it harder to extend your CPU. Often not worth it to optimize this too much
  • Exact details left for Project 3B

29

CS 61C

Summer 2025

30 of 58

Complete RISC-V Datapath!

30

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

CS 61C

Summer 2025

31 of 58

Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

31

CS 61C

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Complete RISC-V Datapath

32

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

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[Practice] RV32I Datapath and Control

For each instruction below:

  1. Which wires should hold relevant data, i.e., what is the “lit up” datapath?
  2. What should the control signals be set to?
  3. Does this instruction use all 5 phases?

​

  1. add rd rs1 rs2
  2. beq rs1 rs2 offset
  3. sw rs2 imm(rs1)
  4. lw rd imm(rs1)

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34

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

  1. add rd rs1 rs2
  2. beq rs1 rs2 offset
  3. sw rs2 imm(rs1)
  4. lw rd imm(rs1)
  • Which wires should hold relevant data?
  • What should the control signals be set to?
  • Does this instruction use all 5 phases?

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  • add rd rs1 rs2
  • beq rs1 rs2 offset
  • sw rs2 imm(rs1)
  • lw rd imm(rs1)
  • Which wires should hold relevant data?
  • What should the control signals be set to?
  • Does this instruction use all 5 phases?

Scratch Work:

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Control Logic Truth Table (Partial)

36

inst[31:0]

BrEq

BrLT

PCSel

ImmSel

BrUn

ASel

BSel

ALUSel

MemRW

RegWEn

WBSel

R-Type

*

*

+4

*

*

Reg

Reg

(Op)

Read

1

ALU

add

​

​

​

​

​

​

​

Add

​

​

​

sub

​

​

​

​

​

​

​

Sub

​

​

​

addi

*

*

+4

I

*

Reg

Imm

Add

Read

1

ALU

lw

*

*

+4

I

*

Reg

Imm

Add

Read

1

Mem

sw

*

*

+4

S

*

Reg

Imm

Add

Write

0

*

beq

​

​

​

B

*

PC

Imm

Add

Read

0

*

not taken

0

*

+4

​

​

​

​

​

​

​

​

taken

1

*

ALU

​

​

​

​

​

​

​

​

bne

​

​

​

B

*

PC

Imm

Add

Read

0

*

taken

0

*

ALU

​

​

​

​

​

​

​

​

not taken

1

*

+4

​

​

​

​

​

​

​

​

blt taken

*

1

ALU

B

0

PC

Imm

Add

Read

0

*

bltu taken

*

1

ALU

B

1

PC

Imm

Add

Read

0

*

jalr

*

*

ALU

I

*

Reg

Imm

Add

Read

1

PC+4

jal

*

*

ALU

J

*

PC

Imm

Add

Read

1

PC+4

auipc

*

*

+4

U

*

PC

Imm

Add

Read

1

ALU

Do Project 3!

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Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

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Two Options for Control Realization

  • Read-Only-Memory (ROM)
    1. Regular structure
    2. Can be easily reprogrammed to…
      1. fix errors
      2. add instructions
    3. Popular when designing control logic manually
  • Combinational Logic
    • Instead of ROM, design with gates (AND, OR, NOT)
    • Popular for chip design (fast)
    • Today, chip designers use logic synthesis tools to convert truth tables to networks of gates.

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RV32I ROM-based Control

  • Read-Only-Memory (ROM) reads out a word at a given address.
  • To get control signals:
    • Input Address: Relevant set of instruction bits
    • Output word: Bits of control signals

39

1. What is the minimum set of instruction bits needed for input (RV32I)?

2. Why might PCSel not be known at this time?

A. 32

B. 17

C. 11

D. 9

E. Something else

(address)

?

decoder

ROM

control signals

RegWEn

ImmSel[2:0]

BrUn

BSel

ASel

ALUSel[3:0]

MemRW

WBSel[1:0]

control word

14

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RV32I is a “9-bit ISA”

  • inst[30]
    • funct7
    • add/sub, sll/srl
  • inst[14:12]
    • funct3
  • inst[6:2]
    • opcode
    • inst[1:0] fixed in RV32I, changes with extensions (e.g., compressed instructions)

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RV32I ROM-based Control

41

9

inst[30,� 14:12,

6:2]

decoder

ROM

RegWEn

ImmSel[2:0]

BrUn

BSel

ASel

ALUSel[3:0]

MemRW

WBSel[1:0]

14

BrEq

Datapath

BrLT

Datapath

Control Logic Part 1

Take branch?

PCSel

Control Logic Part 2

PCSel cannot be encoded in our ROM because it depends on subsequent datapath output (branch comparator).

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ROM Controller Implementation

Under the hood, the ROM controller can be implemented as combinational logic gates. Use Sum of Products on logic table.

42

ROM

Control Word for add

Control Word for sub

Control Word for or

…

…

decoder

add

or

jal

9

inst[30,� 14:12,

6:2]

14

control word

AND

OR

sub

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Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

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Combinational Logic-based Control Logic

  • Much harder than ROM approach
    • We won't be able to help as much in OH
  • But also lets you see the beauty of RISC-V's underlying design
  • Goal: Build a combinational logic circuit that computes each individual control signal, using the 9 relevant bits of the opcode and funct3/funct7
  • Compared to a ROM or comparator-based approach, uses significantly fewer gates (1000+ vs 25 gates)

44

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[Practice] Combinational Logic-based Control Logic

  • Write boolean expressions for:
    • BrUn
    • ASel
    • BSel
    • RegWEn
    • You can do more too!

45

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[Practice] Write a Boolean Expression for BrUn

46

Instruction

Opcode

Funct3

beq rs1 rs2 label

110 0011

000

bne rs1 rs2 label

110 0011

001

blt rs1 rs2 label

110 0011

100

bltu rs1 rs2 label

110 0011

110

bge rs1 rs2 label

110 0011

101

bgeu rs1 rs2 label

110 0011

111

31 25 24 20 19 15 14 12 11 7 6 0

B

imm[12|10:5]

rs2

rs1

funct3

imm[4:1|11]

opcode

BrUn = !inst[2]&!inst[3]&!inst[4]&inst[5]&inst[6]&inst[13]

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[Practice] Write a Boolean Expression for BrUn

47

Instruction

Opcode

Funct3

beq rs1 rs2 label

110 0011

000

bne rs1 rs2 label

110 0011

001

blt rs1 rs2 label

110 0011

100

bltu rs1 rs2 label

110 0011

110

bge rs1 rs2 label

110 0011

101

bgeu rs1 rs2 label

110 0011

111

31 25 24 20 19 15 14 12 11 7 6 0

B

imm[12|10:5]

rs2

rs1

funct3

imm[4:1|11]

opcode

BrUn = inst[13]

For non-Branch instructions, BrUn is *, not 0. So we don't actually need to check the opcode bits!

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Combinational Logic-based Control Logic

  • Much harder than ROM approach
    • We won't be able to help as much in OH
  • But also lets you see the beauty of RISC-V's underlying design
  • Goal: Build a combinational logic circuit that computes each individual control signal, using the 9 relevant bits of the opcode and funct3/funct7
  • Compared to a ROM or comparator-based approach, uses significantly fewer gates (1000+ vs 25 gates)
  • General approach: Find patterns in instructions, take advantage of * values to minimize circuit complexity. Handle each bit separately.

48

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Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing

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Instructions' Critical Path

For each of the below instructions, what is the delay along the critical path?

1. add rd rs1 rs2

2. lw rd imm(rs1)

​

50

A. tclk_q + tAdd + tIMEM + tReg� + tBrComp + tALU + tDMEM + tmux + tSetup

B. tclk_q + tIMEM + tReg + tmux� + tALU + tmux + tsetup

C. tclk_q + tIMEM + max{tReg, tImm}� + tALU + 2*tmux + tDMEM + tSetup

D. tclk_q + tIMEM + max{tReg, tImm}� + tALU + 3*tmux + tSetup

E. Something else

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Critical Path for Add: tclk_q + tIMEM + tReg + tmux

+ tALU + tmux + tsetup

51

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

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Critical Path for lw: tclk_q + tIMEM + max{tReg, tImm} + tALU + 2*tmux + tDMEM + tSetup

​

52

PC

dataR

addr

​

IMEM

​

dataW

rsW

rs1 data1

rs2

data2�

Reg[]

+

4

Control Logic

A

ALU

B

ImmGen

1

0

dataR

addr

DMEM

dataW

1

0

0

1

1

0

2

Branch Comp

PC Sel

ALUSel

ASel

MEMRW

WBSel

RegWEn

BSel

ImmSel

BrUn

BrLt

BrEq

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Instruction Timing, Divided by 5 Phases

  • To estimate maximum clock frequency, analyze at a higher level.
  • Assume each phase is dominated by major functional HW units:

53

Instruction Decode (IF)

Execute (EX)

Instruction Fetch (IF)

Memory Access (MEM)

Write back to Reg (WB)

200 ps

100 ps

200 ps

200 ps

100 ps

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Compute Clock Period

  • The clock cycle must encompass the longest critical path delay incurred by any instruction.

54

Instruction

IF (200ps)

ID (100ps)

EX (200ps)

MEM (200ps)

WB (100ps)

Total

add

X

X

X

​

X

600ps

beq

X

X

X

​

​

500ps

jal

X

X

X

​

​

500ps

lw

X

X

X

X

X

800ps

sw

X

X

X

X

​

700ps

  • Maximum Clock Frequency:
    • fmax = 1/800 ps = 1.25 GHz
    • However, not all instructions use all HW blocks.
  • Many blocks are idle most of the time…!
    • Conversely, each phase just takes 200 ps → could clock 5GHz…??

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5-Phase Timing, In Detail

55

PC

clock

Instr. fetch

Instr. decode

Execute

Memory Access

pc

pc+4

old

old

old

old

old

instruction

register out

ALU result

memory data

tIF

tID

tEX

tMEM

tWB

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Agenda

  • Implementing Branches
  • Implementing U-types
  • Implementing ImmGen
  • Datapath and Control
    • Control Logic Design: ROM
    • Control Logic Design: Combinational Logic
  • Instruction Timing
  • And in Conclusion

56

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Call home, we’ve made HW/SW contact!

57

High Level Language�Program (e.g., C)

Assembly Language �Program (e.g., RISC-V)

Machine Language Program (RISC-V)

Hardware Architecture Description�(e.g., block diagrams)

Logic Circuit Description�(Circuit Schematic Diagrams)

Compiler

Architecture Implementation

Assembler

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

1000 1101 1110 0010 0000 0000 0000 0000

1000 1110 0001 0000 0000 0000 0000 0100

1010 1110 0001 0010 0000 0000 0000 0000

1010 1101 1110 0010 0000 0000 0000 0100

lw x3, 0(x10)

lw x4, 4(x10)

sw x4, 0(x10)

sw x3, 4(x10)

IMEM

ALU

Imm

.

Gen

+4

DMEM

Branch

Comp.

Reg

[]

AddrA

AddrB

DataA

AddrD

DataB

DataD

Addr

DataW

DataR

1

0

0

1

2

1

0

pc

0

1

inst

[11:7]

inst

[19:15]

inst

[24:20]

inst

[31:7]

pc+4

alu

mem

wb

alu

pc+4

Reg

[rs1]

pc

imm

[31:0]

Reg

[rs2]

wb

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“And in conclusion…”

  • We have built a processor!
    • Capable of executing all RISC-V instructions in one cycle each
  • Not all HW units used by all instructions
    • The critical path changes based on instruction.
  • 5 Phases of execution
    • IF, ID, EX, MEM, WB
    • Not all instructions are active in all phases
  • Controller specifies how to execute instructions
    • Implemented as ROM or logic
  • Next:
    • Making our single-stage CPU faster

CS 61C

Summer 2025