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MAPredict: Static Analysis Driven Memory Access Prediction Framework for Modern CPUs and GPUs

Scientific Achievement

We developed a static analysis-driven memory access prediction framework, called MAPredict, with which we could identify the similarities and dissimilarities in the memory traffic patterns of various applications on different generations of Intel CPUs, NVIDIA GPUs, and AMD GPUs.

Significance and Impact

Cache hierarchy is a significant role in deciding the compute and memory intensity of a program. Exploring when and why a last-level cache (LLC)-memory transaction occurs is essential to understanding the performance on modern CPUs and GPUs. This study presents an approach to explore and understand the impact of memory-access patterns on various Intel CPUs, NVIDIA GPUs, and AMD GPUs.

Workflow of MAPredict framework. The MAPredict framework automatically generates a memory access prediction model for a given input application via compile-time static analysis. The generated memory access prediction model can be used for various performance prediction studies for the given application on diversely heterogeneous target systems.

Technical Approach

Investigate and compare four Intel CPUs (Broadwell, Skylake, Cascade Lake, Cooper Lake), three NVIDIA GPUs (P100, V100, A100), and three AMD GPUs (MI50, MI60, MI100), for different memory access patterns.
Develop a static analysis-driven framework named MAPredict to predict LLC-DRAM traffic at compile time.

M. A. H. Monil, S. Lee, J. S. Vetter, and A. D. Malony, MAPredict: Static Analysis Driven Memory Access Prediction Framework for Modern CPUs, the ISC High Performance (ISC 2022), 2022.

PI(s): Robert Ross (ANL); Local Lab POC: Seyong Lee (ORNL)

Collaborating Institutions: ORNL, University of Oregon

ASCR Program: SciDAC RAPIDS2 ASCR PM: Kalyan Perumalla

Publication for this work: M. A. H. Monil, et al., “Static Analysis Driven Memory Access Prediction Framework for Modern CPUs”, the ISC High Performance (ISC 2022), 2022.

DOI: 10.1007/978-3-031-07312-0_12

LOCAL LAB POC: Seyong Lee (ORNL)

TALKING POINTS:

Cache hierarchy is a significant role in deciding the compute and memory intensity of a program.
Exploring when and why Last Level Cache (LLC)-memory transaction occurs is essential to understanding the performance on modern CPUs and GPUs.
This study presents an approach to explore and understand the impact of memory-access patterns on various Intel CPUs, NVIDIA GPUs, and AMD GPUs.
We investigate and compare four Intel CPUs (Broadwell, Skylake, Cascade Lake, Cooper Lake), three NVIDIA GPUs (P100, V100, A100), and three AMD GPUs (MI50, MI60, MI100), for different memory access patterns.
We develop a static analysis-driven framework named MAPredict to predict LLC-DRAM traffic at compile time.
We evaluate the LLC-memory traffic prediction accuracy of MAPredict for Intel CPUs and NVIDIA GPUs and AMD GPUs.

METADATA:

Project: SciDAC RAPIDS2

PI name(s): Rob Ross (ANL), Scott Klasky (ORNL)
Name of the program manager: Supporting technology supported by ASCR research (Kalyan Perumalla)

Project: DOD Brisbane

PI name: Jeffrey S. Vetter (ORNL)

CITATIONS:

M. A. H. Monil, S. Lee, J. S. Vetter, and A. D. Malony, MAPredict: Static Analysis Driven Memory Access Prediction Framework for Modern CPUs, the ISC High Performance (ISC 2022), 2022. (DOI: 10.1007/978-3-031-07312-0_12)
Mohammad Alaul Haque Monil, Seyong Lee, Jeffrey S. Vetter, and Allen D. Malony, Comparing LLC-memory Traffic between CPU and GPU Architectures, RSDHA: Redefining Scalability for Diversely Heterogeneous Architectures, in conjunction with SC21, 2021. (DOI: 10.1109/RSDHA54838.2021.00007)