1 of 7

Lighting the AUIPC Datapath (6/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

Add PC + imm!

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

Write result to destination register.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

Generate imm with upper 20 bits. (U-Type)

Don’t write to memory.

(unselected data lines omitted from lighting)

ASel

1

​

ALUSel

Add

PCSel�not taken(0)

ImmSel

U

RegWEn�1

BrUn

*

BSel

1

WBSel

1

MemRW

Read

2 of 7

Lighting the AUIPC Datapath (1/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

inst[31:7]

(unselected data lines omitted from lighting)

3 of 7

Lighting the AUIPC Datapath (2/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

(unselected data lines omitted from lighting)

4 of 7

Lighting the AUIPC Datapath (3/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

Generate imm with upper 20 bits. (U-Type)

(unselected data lines omitted from lighting)

ImmSel

U

5 of 7

Lighting the AUIPC Datapath (4/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

Generate imm with upper 20 bits. (U-Type)

(unselected data lines omitted from lighting)

ASel

1

​

ALUSel

Add

PCSel�not taken(0)

ImmSel

U

RegWEn�1

BrUn

*

BSel

1

WBSel

1

MemRW

Read

6 of 7

Lighting the AUIPC Datapath (5/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

Add PC + imm!

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

Generate imm with upper 20 bits. (U-Type)

(unselected data lines omitted from lighting)

ASel

1

​

ALUSel

Add

PCSel�not taken(0)

ImmSel

U

RegWEn�1

BrUn

*

BSel

1

WBSel

1

MemRW

Read

7 of 7

Lighting the AUIPC Datapath (6/6)

A

ALU

B

Branch Comp.

add

PC

R[rs1]

rdata

addr

DMEM

wdata

clk

clk

clk

alu

R[rs2]

imm[31:0]

+4

mem

pc+4

alu

inst[31:0]

BrEq

BrLT

Control Logic

wdata

rd

rs1 rdata1

rs2

rdata2

RegFile

Add PC + imm!

pc+4

Imm. Gen

2

1

0

addr

inst

​

IMEM

1

0

Increment PC to next instruction.

Write result to destination register.

0

1

0

1

inst[11:7]

inst[19:15]

inst[24:20]

pc

pc

inst[31:7]

Generate imm with upper 20 bits. (U-Type)

(unselected data lines omitted from lighting)

ASel

1

​

ALUSel

Add

PCSel�not taken(0)

ImmSel

U

RegWEn�1

BrUn

*

BSel

1

WBSel

1

MemRW

Read

Don’t write to memory.