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SERVER

OCP NIC Community Update�March 2024

�����Sub-group Project wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

NIC3.0

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Agenda

  • DSFF specification updates
  • Mechanical tolerance analysis update
  • Mechanical workstream call to action
  • SI workstream update

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DSFF Power Topologies

  • Keep single +12V_EDGE power domain
      • Management on Primary Connector
      • Shared board side power supplies
      • Reduced power supply area
      • BOM cost reduction
      • As-is in spec today

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  • Remove split +12V_EDGE from card side
      • Duplicated NIC rail voltages
      • Additional BOM cost
      • More complex baseboard sde implementation

Examples only. One or more network controllers permissible for each power domain.

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DSFF Card Edge Downshifting

  • Use single DSFF card outline
      • Card edge features must be present
      • Gold pads may be reduced if not using all x32 lanes / cost savings.
          • OK to detect DSFF with PRSNTB[0:3] when plugged into single connector HPM
          • Use all PRSNTB[0:7] pins in dual conn HPM
          • Re-evaluate impact on connector if pushing against PCB material vs gold pad.

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  • No card edge feature downshifting in DSFF
      • SFF / LFF allowed this

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LFF Content - Move to Appendix

  • LFF has not been adopted by major baseboard and NIC vendors.
  • Suggest moving LFF content to Appendix

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LFF has been in the spec since the initial drafts.

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Mechanical workgroup meeting 2/26/2024: OK to move to appendix.

Electrical workgroup meeting 2/26/2024: OK to move to appendix.

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Move to appendix after March 6th public meeting

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Insulator Keep out Zone

  • Insulator keep out zone is clearly defined in the spec today – 14.06 mm from edge of PCB
  • PCIe AC caps far away from board edge. Not good use of space for PCB.

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Request

  • Mechanical WG investigate reduction of secondary side insulator adhesive keep out zone.
  • Minimize attachment points to “keyway” areas only? (in red)

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Mechanical workgroup meeting 2/26/2024: 14.06 mm keep out defined as-is for potential for vertical card tilt on insertion. Prevents secondary side components from being sheared off.��Potential to define tighter rail guide tolerances or limit maximum component height in this region (e.g. 0402’s only). Needs follow up analysis.

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Mechanical tolerance analysis update

TE completed tolerance analysis similar to Amphenol's

  • Analysis included true position tolerance as part of analysis, DPPM varied slightly due to this but still in agreement with initial analysis

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  • TE analysis agrees with Amphenol recommendation to increase AIC slot width from 1.85mm to 2.1mm

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Mechanical workstream call to action

  • Workstream participation has been varied
  • Need commitment and help to complete key tasks
  • Owners need for:
    • Face plate creation
      • Internal latch
      • External latch
    • Detailed drawings
    • Thermal model
    • Thermal test fixture
    • Shock and vibe test fixture

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SI Workstream Goals

  • Align DSFF to PCIe® Gen 4, 5, 6 limits or modify for OCP form factors
  • OCP NIC 3.0 card channel budget defined from gold finger edge to end point silicon
  • This workstream should factor the following use cases
    • Consider DC-MHS HPM/motherboards as well as vendor specific (non-OCP) systems
    • Slots shall be backward compatible to SFFs
    • Various SFF & DSFF configurations (ex. 2 SFFs <->1 DSFF -vs- purpose build for DSFF only)
    • 1st DSFF NICs may use PCIe Gen 4/5 ASICs, with PCIe Gen 6 DSFFs approaching fast

Disclaimer: Current working material restricted by the OCP CLCA

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Intel simulated DSFF board route

  • Note this is an initial representative routing study with 32 lanes
  • -7dB insertion loss target assumes ultra low-loss material and adherence to strict board routing to control loss
  • Blue rectangular regions indicate the secondary side pkg keep out. PCIe AC caps placed north of this zone
  • Route assuming PCIe region of ASIC is centered, this may not necessarily be the best position for thermals
  • PCIe routes do not account for nearby heatsink mount holes

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SI Call to Action

  • GOAL: Release PCIe Gen 5 limits into the next v1.4 draft spec by 3/19
  • Review working material and the workstream’s converging proposal for the PCIe Gen 5 loss limit target: -7.0 dB @ 16 GHz for DSFF

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  • Several companies have contributed values; seeking others’ inputs
  • Once Gen 5 is drafted, the workstream will shift focus onto PCIe Gen 6 studies

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Latest Draft Spec

See wiki page:

https://www.opencompute.org/w/index.php?title=Server/NIC#Working_Draft_Docs

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