Lecture 03 - PCB Layout

Turning schematics into boards

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Outline

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

• PCB structure
• Components
• Layout tools
• Design Flow
• Routing and placement considerations
• Traces
• Integrated circuits
• Board
• Interfaces
• Examples

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

How were Printed Circuit Boards conceived?

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Electronics Before PCBs

Point-to-point

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

A common method for wiring was a simple point-to-point connections

• Components mounted to an enclosure with wires soldered to each to provide connections
• A little messy

https://www.psaudio.com/blogs/pauls-posts/pcb-vs-point-to-point

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Electronics Before PCBs

Wire wrap

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.hackster.io/ss5r/wire-wrapping-not-just-a-guide-f3fc74

https://www.nutsvolts.com/magazine/article/wire_wrap_is_alive_and_well

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Electronics Before PCBs

Breadboards and Perfboards

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.bcae1.com/circuitboardetch.htm

https://learn.sparkfun.com/tutorials/how-to-use-a-breadboard/why-use-breadboards

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Electronics Before PCBs

Manhattan and Dead Bug Style

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://makezine.com/article/technology/a-fine-example-of-dead-bug-style-circuit-wiring/

https://nomadic.blog/2015/08/19/initial-attempts-at-manhattan-construction-and-a-tone-generator/

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Inventing the PCB

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

How can we make circuit construction more efficient and compact?

• Generally fine with having components on a flat board with an assembly built around it
• Have well developed lithographic industrial processes
• For lower power electronics, do not need much conductor to connect components to together
• Often have one contiguous return path (ground) in our design

​

Gives us an idea…

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Inventing the PCB

Single-Sided Board (Muppet Style)

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Similar to Manhattan Style, we use a non-conductive substrate laminated with a sheet of copper. Traces are cut out to connect components together

• We create pads for devices to be soldered to
• The copper regions around the traces can act as one large ground plane

​

We can do better!

https://www.amateurradio.com/manhattan-style/

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Inventing the PCB

Double-Sided Board

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.amateurradio.com/manhattan-style/

We add a sheet of copper to the other side and cut traces

• Adds an additional plane by which to route connections
• Traces can be cross each other on either side

But this leaves us with two electrically isolated circuits.

How do we connect traces from one layer to the other?

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Inventing the PCB

Vias

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://resources.altium.com/p/changing-pcb-reference-planes-during-routing-multilayer-boards

We take the end of a trace on one side of the board and drill a hole through it and the end of another trace on the other side of the board, then plate that hole with metal

• Creates an electrical connection that spans across layers
• Known as a via
• Large holes can be used to mount plated through-hole (PTH) components

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Inventing the PCB

Soldermask

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.researchgate.net/figure/Coarse-PCB-pieces-a-before-the-removal-of-solder-mask-and-b-after-the-removal-of_fig7_355368696

To protect the board during assembly and from corrosion, a non-conductive coating (soldermask) is applied to copper that is not to be soldered to

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Inventing the PCB

Surface Finish

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.setgmbh.de/en/technology/plated-through-slots-and-sideplating

Copper that is not covered by soldermask (usually pads that will be soldered to later), is plated with metal to prevent corrosion and improve solderability. Common plating types:

• ENIG (gold plating)
• HASL (solder plating)
• ENEPIG (palladium/gold plating)
• ImAg (silver plating)
• ImSn (tin plating)
• OSP (organic cover)

​

​

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Inventing the PCB

Silkscreen

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.pcbgogo.com/blog/What_Is_Silkscreen_On_a_PCB_.html

Text and markings can be added on top of soldermask with non-conductive ink (silkscreen). Critical for marking component locations and orientations

https://resources.altium.com/p/your-guide-pcb-silkscreen

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Inventing the PCB

Putting It All Together

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Substrates and their copper laminates can be stacked together to create multilayer PCBs, with layers connected to another using vias.

• Typically 2-20 conductive layers
• The non-conductive substrates are known as dielectrics which can range in materials depending on the application
• Soldermask/surface finish/silkscreen on top and bottom

https://morepcb.com/8-layer-pcb-stack-up/

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Inventing the PCB

Example

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://opencircuitsbook.com/#book-14

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• 4 layers
• 2 inner plane layers
• 2 outer signal layers
• Large core with smaller prepreg
• Likely FR4
• Red soldermask
• White silkscreen
• Through vias

Inventing the PCB

Example

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://opencircuitsbook.com/#book-16

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• HDI Board
• 10 layers
• Thorough mix of plane and signal layers
• Very thin prepreg and core
• Blind vias
• Connects internal layers
• Not required to drill through entire board
• Micro vias
• Very small diameter

Inventing the PCB

Components

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Many components are made to be mounted on top of PCBs using Surface Mount Technology (SMT)

​

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-tinyrad.html#eb-overview

https://electronicslovers.com/2018/10/surface-mount-electronic-components-and-their-types.html

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SMT Components

Two-Lead Passive Chip Components

Chip capacitors, inductors, and resistors come in standard sizes

• Each size defines a standard copper pad design (footprint) that can be used on the board
• Imperial code is more often used

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

First two digits: approx. length

Last two digits: approx. width

https://www.doeeet.com/content/eee-components/passives/five-not-so-general-purpose-mlcc/

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SMT Components

Multi-lead Integrated Circuits

Come in many different packages:

• SOP, SOIC, TSSOP, QFP have splayed pins that extend beyond the package
• QFN, DFN, MLF have pins on the side of the package, but they do not protrude
• BGA, WLP, LGA, CSP have pins located and soldered on the bottom of the package

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://learn.sparkfun.com/tutorials/integrated-circuits/all

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SMT Components

Multi-lead Integrated Circuits

​

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://learn.sparkfun.com/tutorials/integrated-circuits/all

Dot or notch on the corner of IC refers to pin 1

https://www.infineon.com/cms/en/product/packages/PG-TSSOP/PG-TSSOP-16-8/

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SMT Components

Diodes

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://etstore.in/index.php/product/1n4148w-t4-smd-fast-switching-diode-sod-123-75v-150ma/

Notched side of an SMT diode refers to its cathode

https://www.railwayscenics.com/our_leds.php

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SMT Components

Footprints

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

All components (as represented by a symbol in schematic) will require a footprint in order to be mounted onto a PCB. This will contain:

1. Cutouts for pins to be soldered to
2. Markings to show orientation (i.e. pin 1 dot)
3. Thermal pad/vias
4. Other labels/designators

These specifications are typically defined in manufacturer’s datasheet

https://www.chipquik.com/store/product_info.php?products_id=3100182

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SMT Components

Footprints

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.chipquik.com/store/product_info.php?products_id=3100182

Footprints also allow us to specify solder stencils

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SMT Components

Solder Paste

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://bltcircuitservices.co.uk/product/hg1-no-clean/

Contains small beads of solder suspended in a liquid flux carrier.

When heated, flux cleans pad and burns away while the solder melts onto the pad

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SMT Components

Solder Paste

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.solder.net/products/stencilmate-leadless-device-rework-stencils/

https://hackaday.com/2022/10/02/making-a-handheld-nes-by-turning-dip-chips-into-qfn/

Bad reflow

Good reflow

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SMT Components

Reflow and Soldering Process

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

1. PCB is laid flat and clean
2. Stencil is secured on top and aligned with pads
3. Solder paste is applied and spread over the stencil
4. Stencil is removed
5. SMT components are placed on their respective pads
6. PCB is reflowed (oven, hot plate, hot air)
7. Through-hole components are manually placed and soldered by hand

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

How do we layout PCBs?

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Layout Tools

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Given a schematic, how do we convert it into a board that fulfills our requirements?

LAYOUT

?

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Layout Tools

Layer Stack Definition

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Define board manufacturing parameters including:

• Number of layers
• Thickness
• Substrate dieletric type
• Surface finishes and soldermask

​

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Layout Tools

Board Shape

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Layout Tools

Rooms

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Layout Tools

Routing

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Layout Tools

Copper Pours

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Layout Tools

Vias

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Layout Tools

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

The aforementioned layout features are combined with Design Rule Checks (DRC) to define a board layout�DRC provides verification during layout that certain rules are met as defined by the user. These include:

• Minimum clearance between traces, components, and board edge
• Trace width bounds
• Pads are connected to the correct nets

Warning messages are provided in a user-generated report or actions can be outright prevented during a DRC violation

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Design Flow

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Demo

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Announcements

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Please fill out our week 1 survey!

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Link also in #announcements

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Backup

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Routing and Placement Considerations

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Routing and Placement Considerations

Maxwell’s Equations

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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Charges produce an electric field

Magnetic field lines never end

Changing magnetic field induces electric field

Bulk and changing electric field induces magnetic field

Routing and Placement Considerations

Maxwell’s Equations

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

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• Stray charges and fields can induce undesired currents/voltages in a circuit
• As a circuit’s operating frequency increases and size decreases, electromagnetic susceptibility becomes a greater issue
• High currents creates heat in conductors (electron collisions)

​

Routing and Placement Considerations

Trace width and length

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.protoexpress.com/blog/trace-current-capacity-pcb-design/

• Trace cross section (width and thickness) determines current-carrying capability and resulting temperature rise (keep < 10^OC rise)
• Use polygon pours in place of traces for high current nets
• Keep traces as short as possible to avoid voltage drops and signal distortions
• For long traces, avoid creating loops to prevent capture of external magnetic flux

​

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Routing and Placement Considerations

Trace Spacing

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

• PCB fabricators have limits to how close they can manufacture two traces next to each other. These clearance minimums must be met to avoid tolerance errors
• For high voltage traces, electric breakdown in the dielectric or air can cause shorts, proper spacing is required
• Keep high frequency and noisy traces separate from other traces. Fields generated by these can induce currents in other traces

​

https://docs.oshpark.com/services/two-layer/

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Routing and Placement Considerations

Trace Spacing

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

High frequency (RF and high speed digital) traces often have special routing requirements that govern trace width and clearance, typically to maintain a particular impedance throughout

Differential traces consist of two of such traces with the additional requirement of needing to be routed next to and symmetric to each other as well as having the same length

• Differential traces have improved common-mode noise immunity over single-ended traces

​

​

https://www.allaboutcircuits.com/technical-articles/the-why-and-how-of-differential-signaling/

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Routing and Placement Considerations

Trace Shape

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

For most traces, cornering style does not matter.

However, high frequency traces will require smooth bends or chamfered corners

Commonly seen on many boards, often preferred for low frequency signals

Good for sharp turns with high frequency signals

Best for high frequency signals

Fine for low frequency applications, should generally avoid

Chamfered corner for impedance matching

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Routing and Placement Considerations

Decoupling ICs

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.protoexpress.com/blog/decoupling-capacitor-use/

Decoupling capacitors are placed near the power input pins of ICs and provide filtering of noise and transients

Typically, a large- and small-valued capacitor combination is used as close to the IC as possible. (e.g. 100 nF and 200 pF)

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Routing and Placement Considerations

Thermal Pads and Vias

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Many ICs will contain thermal pads

Often recommended to add thermal vias to the pad

These allow heat to dissipate to other layers and provide additional grounding

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Routing and Placement Considerations

Thermal Reliefs

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Often pads (particularly PTH) will be difficult to hand-solder to as the heat from the soldering iron will transfer through the traces and ground pours connected to the pad.

Thermal reliefs solve this issue by removing copper around the pad to limit heat transfer while maintaining an electrical connection

https://www.protoexpress.com/blog/use-thermal-pads-pcb-design-manufacturing/

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Routing and Placement Considerations

Thermal Reliefs

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Without thermal reliefs

With thermal reliefs

Thermal reliefs improve hand solderability but reduce return path connection

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Routing and Placement Considerations

Power Planes

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

In a multilayer board, parts of or entire internal layers can be assigned to specific power nets to form a power plane

Vias can be used for devices (typically on the top or bottom layers) to easily access a power net

• Reduces number of traces
• Limits power losses
• Isolates noisy power nets

http://www.elmac.co.uk/EMC_SelfStudy-std/Index.htm?context=380

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Routing and Placement Considerations

Ground Pours

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Like power planes, entire layers should be dedicated to the ground net to create a low-impedance return path

Empty regions should be filled with ground pours to further provide short return path and reduce fringing fields

Ensure all regions of a copper ground pour are connected together; via stitching can help ensuring ground pours are connected well

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-HMC703LP4E.html

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Routing and Placement Considerations

Separate Ground Planes

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Sometimes we do want poorly connected ground planes

• When high speed digital and high frequency analog circuits are located on the same board

Separate ground planes that are poorly connected to each other as well as careful placement, can isolate noise and prevent each from interfering with the other.

http://www.elmac.co.uk/EMC_SelfStudy-std/Index.htm?context=380

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Routing and Placement Considerations

Separating Circuits

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

A good practice is to separate the various functional blocks in the schematic into their own physical blocks in layout.

• Each block is typically its own sheet in schematic
• Simplifies reuse of functional blocks
• Easy to follow when debugging
• Conforms with many best practices for minimizing interference between circuits on a board

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Routing and Placement Considerations

Edge Effects

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Planes and traces on parallel layers can form inductive loops and capacitors, which create fringing fields on the board edge

Follow 10h rule: high frequency planes and traces should be routed at least a distance of ten times the height of the substrate layer from board edge to avoid effects from fringing fields

Often manufacturers will have a board edge constraint anyways

Top and bottom copper also forms inductive loop that can capture magnetic flux near the edge

https://easyeda.com/forum/topic/The-20H-and-Ground-Plane-Extension-rules-benefits-and-limitations-of-applying-them-4d443d32240545aeb9fa9516d2fdac3f

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Routing and Placement Considerations

Shielding

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Metal shielding around sensitive components can prevent external fields from interfering (particularly electric fields)

Shields should have a generous connection to ground along its perimeter

Highly permeable materials can be used to shield magnetic fields

• Steel and iron are common shielding materials
• Usually will be placed in the enclosure

https://www.crowdsupply.com/microphase-technology/antsdr-e200

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Routing and Placement Considerations

Soldermask Removal

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Soldermask as a dielectric material can create boundary conditions that produce unwanted effects for high frequency circuits

• RF/Microwave circuits will have typically remove soldermask to prevent this

In high power applications, removing soldermask from high-current traces allows solder or a metal block to be attached to increase trace cross section and reduce resistance

Soldermask is removed on traces that need to be carefully impedance controlled

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-HMC788ALP2.html

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Routing and Placement Considerations

Test Points

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Placed on nets where important debugging and test information can be gained

Put many on your PCBs

High frequency circuits requires special care when placing test points as they can cause signal distortions

https://learn.adafruit.com/introducing-the-raspberry-pi-zero/a-tour-of-the-pi-zero

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Routing and Placement Considerations

Connectors

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Both connectors are edge-mount, however the left one is SMT and the right one is PTH

https://www.raypcb.com/pcb-connector/

Connectors allow for external interfacing with a PCB

• Typically mounted on the PCB’s edge
• SMT connectors can delaminate but do not introduce any protrusions on the bottom board side
• Use PTH if possible

SMT

PTH

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Routing and Placement Considerations

Key Takeaways

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

• Segmentize your board: keep digital with digital and analog with analog to best extent you can prevent co-interference
• Ensure there are many debug points, PCBs often do not work first try
• Layout circuits as compactly as possible while maintaining enough space to assemble and debug
• Use ground pours and ground/power planes
• Ensure trace sizing requirements are met for each net
• Choose connectors that are accessible, appropriate for the type of signal they will carry, and will have a strong mechanical connection to the board
• Ensure appropriate mounting points are present

​

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@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

Examples

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Examples

RF/Microwave

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lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-HMC994APM5.html#eb-overview

Evaluation board for a 28 GHz amplifier

• Ground pour throughout, a metal block attached to the bottom to increase ground plane cross section
• Soldermask removed on RF-carrying traces
• Traces made as short as possible
• Many testpoints
• Connectors appropriately selected to handle high frequencies

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Examples

High-Speed Digital

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

135 MHz ADC Evaluation board

• Far separated digital and analog sections
• Separate internal ground plane for digital section
• Differential signals are routed symmetrically
• Contains mounting holes
• Many debug and test points

​

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9694.html#eb-overview

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Examples

High Power

@ MIT

lecture 03 - PCB Layout | pcb.mit.edu | yaypcbs@mit.edu

70 A Buck Converter Evaluation Board

• Wide traces across layers for input and output with via stitches
• Appropriate high current crimped connections for output
• Additional connectors mounted along edge
• No thermal reliefs

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/dc2174a-b.html#eb-overview

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