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R.M.K. ENGINEERING COLLEGE���24EC102 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Lab Integrated)

Department: Electronics and Communication Engineering

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Batch/Year: 2024-2028 / I

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Created by:

Dr. Meena Kumari

Mr. Joel T

Mrs. S. Karkuzhali

Mr. Shyam M

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Date: 1^st November, 2024�

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Table of Contents

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Table of Contents

1. Course Objectives

To acquire the knowledge in Digital fundamentals and its simplification methods.

To familiarize the design of various combinational digital circuits using logic gates.

To realize various sequential circuits using flip flops.

To interpret various clocked sequential circuits.

To elucidate various semiconductor memories and related technology.

To build various logic functions using Programmable Logic Devices.

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20PH102 Physics For Electronics Engineering

2. Pre-requisites

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24EC102 DIGITAL PRINCIPLES AND SYSTEM DESIGN L T P C

3 0 2 4

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9

Review of number systems-representation-conversions, Review of Boolean algebra- theorems, sum of product and product of sum simplification, canonical forms, min term and max term, Simplification of Boolean expressions-Karnaugh map, Implementation of Boolean expressions using logic gates and universal gates.

List of Exercise/Experiments:

1. Implementation of Boolean expression using logic gates.

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UNIT II COMBINATIONAL LOGIC CIRCUITS 9

Design of combinational circuits - Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, Magnitude Comparator, Decoder, Encoder, Priority Encoder, Mux/De-mux, Parity Generator/Checker

List of Exercise/Experiments:

2. Design of adders

3. Design of subtractors.

4. Design of binary adder using IC7483

5. Design of Multiplexers & Demultiplexers.

6. Design of Encoders and Decoders.

7. Implementation of a boolean function using a multiplexer

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UNIT III SEQUENTIAL CIRCUITS 9

Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Asynchronous and Synchronous Counters Design - Shift registers, Universal Shift Register

List of Exercise/Experiments:

8. Design and implementation of 3 bit ripple counters.

9. Design and implementation of 3 bit synchronous counter

10. Design and implementation of shift registers

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3. SYLLABUS

4. Course Outcomes

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After successful completion of the course, the students should be able to

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5. CO – PO /PSO Mapping

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6.1. LECTURE PLAN

UNIT 5: MEMORY AND PROGRAMMABLE LOGIC DEVICES

Total No. of Periods: 9

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6.2. Activity Based Learning

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6.2.1. Quiz

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1. PLA circuit falls in which circuit category?

1. Sequential logic circuit
2. Combinational logic circuit
3. Both Sequential logic circuit and Combinational logic circuit
4. Neither Sequential logic circuit nor Combinational logic circuit

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2. Which type of PLD should be used to program basic logic functions?

1. CPLD
2. PAL
3. PLA
4. SLD

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3. Programmable logic array is a

1. Two Level OR-OR Device
2. Two Level of AND-AND Device
3. Two Level OR-AND Device
4. Two Level AND-OR Device

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4. PLA is programmed to realize any

1. Ex-OR logic expression
2. Product of sum logic expression
3. Sum of products logic expression
4. None of the mentioned

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5. The complex programmable logic device contains several PLD blocks and

1. A language compiler
2. AND/OR arrays
3. Global interconnection matrix
4. Field-programmable switches

6. The memory in which the stored data is lost, when the power is switched off is

1. ROM
2. RAM
3. Ferrite core memory
4. PROM

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7. The advantage of Dynamic RAM over static RAM is

1. Lower power consumption
2. High capacity
3. Low cost per bit
4. All of the mentioned

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8. ROM is costlier, consumes more power and runs slower

1. True
2. False

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9. In which of the following PLD, all Minterms are decoded

1. PROM
2. PLA
3. PAL
4. FPGA

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10. type of memory can read data but can not write data.

1. Random only memory
2. Random – access memory
3. Read – Only memory
4. None of the mentioned

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11. ROM consisting of two of the arrays which are arrays.

1. NOR and OR
2. NAND and NOR
3. NAND and OR
4. NOR and AND

12. Each bit combination that comes out of the output lines, in ROM is called as

1. Memory unit
2. Storage class
3. Data word
4. Address

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13. ROM can be erased by an electrical signal?

1. ROM
2. Mask ROM
3. EPROM
4. EEPROM

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14. PROM is introduced

1. To increase the storage capacity
2. To increase the address locations
3. To provide flexibility
4. To reduce the size

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15. In PROM, MOSFETs used are of

1. Enhancement type n-channel
2. Depletion type n-channel
3. Enhancement type p-channel
4. Depletion type p-channel

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16. The initial values in all the cells of an EPROM is

1. Zero
2. 1
3. Both 0 and 1
4. Alternate 0s and 1s

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17. Static RAM employs

1. BJT or MOSFET
2. FET or JFET
3. Capacitor or BJT
4. BJT or MOS

18. Dynamic RAM employs

1. Capacitor or MOSFET
2. FET or JFET
3. Capacitor or BJT
4. BJT or MOS

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19. The DRAM stores its binary information on

1. MOSFET
2. Transistor
3. Capacitor
4. BJT

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20. Static RAM differs from dynamic RAM because

1. Static RAM must be refreshed, dynamic RAM does not
2. There is no difference
3. Dynamic RAM must be refreshed, static RAM does not
4. SRAM is slower than DRAM

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Quiz – Answers

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1. b
2. c
3. d
4. c
5. c
6. b
7. d
8. a
9. a
10. c
11. c
12. c
13. d
14. c
15. a
16. b
17. d
18. a
19. c
20. c

6.2. Activity Based Learning

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6.3. Lecture Notes

Basic Memory Structure

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• Memory unit is a collection of storage cells with associated circuits needed to transfer information in and out of the device.

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• It stores data or binary information in groups of bits called ‘words.’ Each words

consists of a sequence of 0’s and 1’s.

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• A word may represent a number, an instruction, one or more Alphanumeric characters or any other binary information's.

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• Each word stored in a memory location is represented by an ‘Address’.

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• Group of 8 bits is called as byte.

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• The communication between a memory and its environment is achieved through data input/output lines, Address selection lines and control lines that specify the direction of transfer.

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Memory Unit

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It has k address lines to address or access 2k in the memory

It has n data input output lines through which data is transferred in and out of memory

It has two control inputs called Read and Write.

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Write input causes binary data on I/O line to be transferred into the memory. Read input causes the binary data in a memory location to be transferred out of memory.

The memory unit is specified by the total number of words in it and the number of

bits in each word.

The address line selects one particular word. Each word in memory is assigned an identification number known as address, starting from 0,1,2,3 etc, upto 2k-1.

The selection of a specific word inside the memory unit is done by applying the k bit

binary address to the address lines.

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Memory Types

Read Only Memory (ROM)

ROM is a memory device in which permanent binary information is stored. The binary pattern must be specified by the designer and then embedded in the unit to form the required interconnection pattern.

Once the pattern is established, it stays within the unit even when the power is turned off.

A ROM is programmed for a particular purpose during the manufacturing process

and a user cannot alter its function.

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The memory from which we can only read but cannot write on it. This type of memory is non-volatile.

The information is stored permanently in such memories during manufacture. A ROM stores such instructions that are required to start a computer.

This operation is referred to as bootstrap.

ROM chips are not only used in the computer but also in other electronic items like washing machine and microwave oven.

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Types of ROM

Semiconductor ROMs are manufactured with bipolar or MOS technology. ROMs can be classified into several types which differ as to how information is written or programmed into the memory locations.

Bipolar ROMs use bipolar transistor.

MOS ROM is constructed using MOSFETs.

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MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data or instructions. These kind of ROMs are known as masked ROMs, which are inexpensive.

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PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user

buys a blank PROM and enters the desired contents using a PROM program. Inside the PROM chip, there are small fuses which are burnt open during programming. It can be programmed only once and is not erasable.

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EPROM (Erasable and Programmable Read Only Memory)

EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes. Usually, an EPROM eraser achieves this function. During programming, an electrical charge is trapped in an insulated gate region. The charge is retained for more than 10 years because the charge has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). This exposure to ultra-violet light dissipates the charge. During normal use, the quartz lid is sealed with a sticker.

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EEPROM (Electrically Erasable and Programmable Read Only Memory) EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM, any location can be selectively erased and programmed. EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence, the process of reprogramming is flexible but slow.

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Non-volatile in nature

Cannot be accidentally changed Cheaper than RAMs

Easy to test

More reliable than RAMs

Static and do not require refreshing

Contents are always known and can be verified

The presence of a connection from a row line to the base of a transistor represents 1 at that location.

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When row line is taken high, all transistors with base connection to that row line turn ON and connect the HIGH to the associated column lines.

When there is no base connection, zero value is stored.

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Advantages of ROM

Internal structure of 32 x 8 ROM

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Internal structure of 32 x 8 ROM

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ROM is a combinational logic circuit. It includes decoder and the OR gates within a single IC package.

ROM is characterized by 2ⁿ x m.

In the given example 32 x 8 implies 2⁵ x 8, where 5 represents address lines and 8

represents number of OR gates (output).

This structure has 32 x 8 = 256 internal connections.

The programmable intersection between two lines is called cross-point. Various physical devices are used to implement cross-point switches. One of the familiar technologies is “Fuse” that normally connects the two cross-points (programmable)

Fuses opened are blown by the application of the high voltage pulse into the fuse.

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Qn.1. Design a combinational circuit using ROM. The circuit accepts a 3-bit binary number at the input and generates its square value at the output.

Truth Table

From the Truth Table, output B₁ = 0 and B₀ = A₀. These two outputs are removed from the Truth Table. So in this design, only four outputs are considered. Therefore 8x4 ROM structure is used.

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8 x 4 ROM Structure

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Qn.2. Implement the following Boolean function using ROM. F₁(A, B, C) = Ʃm(0,1,3,4), F₂(A, B, C) = Ʃm(1,2,3,4,5).

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The given functions have three inputs and two outputs. Three inputs need 2³ = 8 possible combinations, since 3:8 decoder is used in this design.

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Truth Table

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Qn.3. Implement a Full adder using ROM.

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The given functions have three inputs and two outputs. Three inputs need 2³ = 8 possible combinations, since 3:8 decoder is used in this design.

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Truth Table

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PROGRAMMABLE LOGIC DEVICES (PLD)

COMBINATIONAL PLD‟S:

• The PROM is a combinational programmable logic device (PLD).
• It is an IC with programmable gates divided into an AND array and an OR array to provide an AND-OR SOP implementation.
• Three major types of combinational PLD‟s :
1. Programmable ROM (PROM)
2. Programmable Array Logic (PAL)
3. Programmable Logic Array (PLA)
• Programmable Read Only Memory: (PROM)
• Fixed AND array constructed as a decoder and a Programmable OR array.
• The programmable OR gates implement the Boolean functions in the sum of minterms.

2. Programmable Array Logic (PAL)
• Programmable AND array and a fixed OR array.
• They implement the Boolean function in SOP.
• AND gates are programmed to give the product terms, which are logically summed in each OR gate.

3. Programmable Logic Array (PLA)
• Most flexible PLD
• Both the AND and OR gates/arrays can be programmed
• The product terms in the AND array may be shared by any OR gate to provide the required SOP implementation.

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Programmable Logic Devices

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• PLD's are devices that can implement a wide variety of logic functions.

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• The programming may be permanent or reprogrammable.

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• Examples of common types of PROM’s:

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• ROM - (Read Only Memory) Is programmed by the manufacturer and cannot be altered by the user (you, engineer)

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• PROM -(Programmable ROM) can be programmed once. These are programmed by frying a set of fuses in the device that permanently break connections between wires. Thus, these devices can not be reprogrammed.

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• EPROM - (Erasable PROM) can be programmed and reprogrammed. To reprogram this device you have to put it under ultraviolet light for an extended period of time.

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• EEPROM - (Electrically Erasable PROM) This device can be erased electrically and is therefore much easier and quicker to work with than a EPROM.

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• The other types of PLD's have similar technologies for programming them

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Common PLD's include

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• PROM's (I'll use this term generically to include all types of PROM’s)

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• PLA's - Programmable Array Logic. This technology is obsolete so I will not discuss it.

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• PAL Devices - Programmable Array Logic Devices. A very popular device for implementing combinational logic, the type that we've been discussing.

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• GAL Devices - Gate Array Logic. Similar to PAL Devices, but these have additional flexibility.

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• PGA - Programmable Gate Arrays. These are even more flexible than GAL’s.

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• FPGA's - Field Programmable Gate Arrays. These devices are very elaborate and can be reprogrammed while being in complete system.

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Logic devices constitute one of the three important classes of devices used to build digital electronics systems, memory devices and microprocessors being the other two. Memory devices such as ROM and RAM are used to store information such as the software instructions of a program or the contents of a database, and microprocessors execute software instructions to perform a variety of functions, from running a word-processing program to carrying out far more complex tasks.

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Logic devices implement almost every other function that the system must perform, including device-to-device interfacing, data timing, control and display operations and so on. So far, we have discussed those logic devices that perform fixed logic functions decided upon at the manufacturing stage.

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Logic gates, multiplexers, demultiplexers, arithmetic circuits, etc., are some examples. Sequential logic devices such as flip-flops, counters, registers, etc., to be discussed in the following chapters, also belong to this category of logic devices. In the present chapter, we will discuss a new category of logic devices called programmable logic devices (PLDs).

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The function to be performed by a programmable logic device is undefined at the time of its manufacture. These devices are programmed by the user to perform a range of functions depending upon the logic capacity and other features offered by the device.

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We will begin with a comparison of fixed and programmable logic, and then follow this up with a detailed description of different types of PLDs in terms of operational fundamentals, salient features, architecture and typical applications. A brief introduction to the devices offered by some of the major manufacturers of PLDs and PLD programming languages is given towards the end of the chapter

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Fixed Logic Versus Programmable Logic

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As outlined in the introduction, there are two broad categories of logic devices, namely fixed logic devices and programmable logic devices. Whereas a fixed logic device such as a logic gate or a multiplexer or a flip-flop performs a given logic function that is known at the time of device manufacture, a programmable logic device can be configured by the user to perform a large variety of logic functions. In terms of the internal schematic arrangement of the two types of device, the circuits or building blocks and their interconnections in a fixed logic device are permanent and cannot be altered after the device is manufactured

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A programmable logic device offers to the user a wide range of logic capacity in terms of digital building blocks, which can be configured by the user to perform the intended function or set of functions.

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This configuration can be modified or altered any number of times by the user by reprogramming the device. Figure shows a simple logic circuit comprising four three-input AND gates and a four-input OR gate. This circuit produces an output that is the sum output of a full adder. Here, A and B are the two bits to be added, and C is the carry-in bit. It is a fixed logic device as the circuit is unalterable from outside owing to fixed interconnections between the various building blocks.

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Programmable Array Logic

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Figure shows the logic diagram of a simple programmable device. The device has an array of four six-input AND gates at the input and a four-input OR gate at the output. Each AND gate can handle three variables and thus can produce a product term of three variables.

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The three variables (A, B and C in this case) or their complements can be programmed to appear at the inputs of any of the four AND gates through fusible links called antifuses. This means that each AND gate can produce the desired three-variable product term. It may be mentioned here that an antifuse performs a function that is opposite to that performed by a conventional electrical fuse.

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Architecture of PAL

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A fuse has a low initial resistance and permanently breaks an electrically conducting path when current through it exceeds a certain limiting value. In the case of an antifuse, the initial resistance is very high and it is designed to create a low-resistance electrically conducting path when voltage across it exceeds a certain level. As a result, this circuit can be programmed to generate any three- variable sum-of-products Boolean function having four minterms by activating the desired fusible links. For example, the circuit could be programmed to produce the sum output resulting from the addition of three bits (the sum output in the case of a full adder) or to produce difference outputs resulting from subtraction of two bits with a borrow-in (the difference output in the case of a full subtractor).

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We can visualize that the logic circuit of Fig has a programmable AND array at the input and a fixed OR gate at the output. Incidentally, this is the architecture of programmable logic devices called programmable array logic (PAL). Practical PAL devices have a much larger number of programmable AND gates and fixed OR gates to have enhanced logic capacity and performance capability. PAL devices are discussed in detail in the latter part of the chapter.

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Advantages and Disadvantages of PLDs

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1. If we want to build a fixed logic device to perform a certain specific function, the time required from design to the final stage when the manufactured device is actually available for use could easily be several months to a year or so. PLD-based design requires much less time from design cycle to production run.

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• In the case of fixed logic devices, the process of design validation followed by incorporation of changes, if any, involves substantial nonrecurring engineering (NRE) costs, which leads to an enhanced cost of the initial prototype device. In the case of PLDs, inexpensive software tools can be used for quick validation of designs The programmable feature of these devices allows quick incorporation of changes and also a quick testing of the device in the actual application environment. In this case, the device used for prototyping is the same as the one that would qualify for use in the end equipment.

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• In the case of programmable logic devices, users can change the circuit as often as they want to until the design operates to their satisfaction. PLDs offer to the users much more flexibility during the design cycle. Design iterations are nothing but changes to the programming file.

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• Fixed logic devices have an edge for large-volume applications as they can be mass produced more economically. They are also the preferred choice in applications requiring the highest performance level.

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Types Programmable Logic Devices

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There are many types of programmable logic device, distinguishable from one another in terms of architecture, logic capacity, programmability and certain other specific features. In this section, we will briefly discuss commonly used PLDs and their salient features. A detailed description of each of them will follow in subsequent sections.

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Programmable ROMs

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PROM (Programmable Read Only Memory) and EPROM (Erasable Programmable Read Only Memory) can be considered to be predecessors to PLDs. The architecture of a programmable ROM allows the user to hardware-implement an arbitrary combinational function of a given number of inputs. When used as a memory device, n inputs of the ROM (called address lines in this case) and m outputs (called data lines) can be used to store 2n m-bit words.

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When used as a PLD, it can be used to implement m different combinational functions, with each function being a chosen function of n variables. Any conceivable n- variable Boolean function can be made to appear at any of the m output lines. A generalized ROM device with n inputs and m outputs has 2n hard-wired AND gates at the input and m programmable OR gates at the output. Each AND gate has n inputs, and each OR gate has 2n inputs. Thus, each OR gate can be used to generate any conceivable Boolean function of n variables, and this generalized ROM can be used to produce m arbitrary n-variable Boolean functions.

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The AND array produces all possible minterms of a given number of input variables, and the programmable OR array allows only the desired minterms to appear at their inputs. Figure shows the internal architecture of a PROM having four input lines, a hard-wired array of 16 AND gates and a programmable array of four OR gates.

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A cross (×) indicates an intact (or unprogrammed) fusible link or interconnection, and a dot (•) indicates a hard-wired interconnection. PROMs, EPROMs and EEPROMs (Electrically Erasable Programmable Read Only Memory) can be programmed using standard PROM programmers. One of the major disadvantages of PROMs is their inefficient use of logic capacity. It is not economical to use PROMs for all those applications where only a few minterms are needed.

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Other disadvantages include relatively higher power consumption and an inability to provide safe covers for asynchronous logic transitions. They are usually much slower than the dedicated logic circuits. Also, they cannot be used to implement sequential logic owing to the absence of flip-flops.

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Programmable Logic Array

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A programmable logic array (PLA) device has a programmable AND array at the input and a programmable OR array at the output, which makes it one of the most versatile PLDs. Its architecture differs from that of a PROM in the following respects. It has a programmable AND array rather than a hard-wired AND array. The number of AND gates in an m-input PROM is always equal to 2m . In the case of a PLA, the number of AND gates in the programmable AND array for m input variables is usually much less than 2m , and the number of inputs of each of the OR gates equals the number of AND gates. Each OR gate can generate an arbitrary Boolean function with a maximum of minterms equal to the number of AND gates.

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Figure shows the internal architecture of a PLA device with four input lines, a programmable array of eight AND gates at the input and a programmable array of two OR gates at the output. A PLA device makes more efficient use of logic capacity than a PROM. However, it has its own disadvantages resulting from two sets of programmable fuses, which makes it relatively more difficult to manufacture, program and test a GAL device can be erased and reprogrammed. Also, it is reprogrammable output logic. This feature makes it particularly attractive at the device prototyping stage, as any bugs in the logic can be corrected by reprogramming. A similar device called PEEL (Programmable Electrically Erasable Logic) was introduced by the International CMOS Technology (ICT) Corporation.

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Programmable Logic Array

Implementation of Boolean Function using Programmable

Logic Arrays

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Qn.1. Implement the following Boolean function using PLA. F1(A,B,C) = Σm(0,1,3,4)

F2(A,B,C) = Σm(1,2,3,4,5).

F1 = B’ C’ + A’ C

F2 = A B’ + A’ C + A’B

PLA Implementation

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PLA Programming Table

Consists of three sections namely product term, inputs and outputs. For each product term, inputs are marked with 1,0, - (dash). If variable present in true form marked with 1. If variable is present in compliment form, marked with 0. If variable is absent marked with dash.

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Qn.2. Implement the following Boolean function using three inputs, four product terms and two outputs using PLA.

F1 = AB’ + AC + A’BC’

F2 = (AC + BC)’

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PLA Programming Table

Consists of three sections namely product term, inputs and outputs. For each product term, inputs are marked with 1,0, - (dash). If variable present in true form marked with 1. If variable is present in compliment form, marked with 0. If variable is absent marked with dash.

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Qn.3. Implement the following Boolean function using 3 x 4 x 2 PLA.

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F1(A,B,C) = Σm(0,1,2,4)

F2(A,B,C) = Σm(0,5,6,7).

F1 and F2 functions have 6 product terms, namely B’C’, A’B’, A’C’, AC, BC and A’B’C’. But implement using four product terms only. So change the K-Map F1 into F’1. That is group 0’s instead 1’s. Now by comparing F’1 and F2, four product terms are obtained, namely AB, AC, BC and A’B’C’.

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PLA Programming Table

Consists of three sections namely product term, inputs and outputs. For each product term, inputs are marked with 1,0, - (dash). If variable present in true form marked with 1. If variable is present in compliment form, marked with 0. If variable is absent marked with dash.

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Qn.4. A combinational circuit is defined by the functions,

F1 (A, B, C) = ∑m (1, 3, 5)

F2 (A, B, C) = ∑m (5, 6, 7)

Implement the circuit with a PLA having 3 inputs, 3 product terms and 2 outputs.

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Qn.5. Design a BCD to Excess-3 code converter and implement using suitable PLA.

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Qn. 6. A combinational circuit is defined by the functions,

Implement the circuit using PAL.

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Qn. 7. Implement FULL Adder using PAL.

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PAL PROGRAMMING TABLE

Comparison between PROM, PLA, and PAL

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1) Implement the following Boolean functions in a PLA: F1 = AB‟ + AC + A‟BC‟

F2 = (AC+BC)‟

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PLA Programming Table

PLA with 3 inputs, 4 products terms and 2 outputs

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PROGRAMMABLE LOGIC ARRAY (PLA)

• A dash specifies a blown fuse.
• An open terminal in the input of an AND gate behaves like a 1.
• An open terminal in the input of an OR gate behaves like a 0

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2) Implement the following Boolean functions with a PLA: F1(A,B,C) = ∑ (0,1,2,4)

F2(A,B,C) = ∑ (0,5,6,7)

Solution:

Simplify using K-Maps

PLA Programming Table

F1 = (AB+AC+BC)‟ F2 = AB+AC+A‟B‟C‟

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AC

BC

A’B’C’

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Implementation using PAL

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w(A, B, C, D) = ∑(2, 12, 13)

x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)

y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)

z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

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Simplifying the four functions as following Boolean functions:

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w = ABC’ + A’B’CD’

x = A + BCD

y = A’B + CD + B’D’

z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D

z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three.

​

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PAL Implementation

PROGRAMMABLE ARRAY LOGIC (PAL)

PROGRAMMABLE ARRAY LOGIC (PAL)

• PAL is a programmable logic device with a fixed OR array and a programmable AND array.
• Easier to program, but is not as flexible as the PLA
• Each input has a buffer-inverter gate and each output has a fixed OR gate.
• Each sections in the unit is composed of a three-wide AND-OR array.
• Unlike the PLA, a product term cannot be shared among two or more OR gates. Therefore, each function can be simplified by itself without regard to common product terms.
• The number of product terms in each section is fixed and if the number of terms in the function is too large, it may be necessary to use two sections.
• If AND gate is not used, all its input fuses are left intact. Since the corresponding input receives both the true and complement of each input variable, we have AA‟

= 0, and the output of the AND gate is always 0.

​

• Implementing Boolean functions with PAL:
• Boolean functions must be simplified to fit into each section.
• A product term cannot be shared among two or more OR gates. So, each function can be simplified by itself without regard to common product terms.

​

1) Implement the Boolean function using a PAL: W(A,B,C,D) = ∑(2,12,13)

X(A.B.C.D) = ∑(7,8,9,10,11,12,13,14,15)

Y(A.B.C.D) = ∑(0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = ∑(1,2,8,12,13)

Simplify using K-Map

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PROGRAMMABLE ARRAY LOGIC (PAL)

PAL Programming Table

Links to Videos and Learning Materials

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6.4. ASSIGNMENTS

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6.5. Part-A: Questions & Answers

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6.6. Part-B: Questions

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6.7. Supportive online Certification courses

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6.8. Real time Applications in day to day life and to Industry

Glue Logic: Glue logic is the Simple logic circuits used to connect together more complex circuits which are not perfectly compatible.  For example, an ASIC chip may contain large functions, such as a microprocessor, memory block or communications block, which are tied together via small amounts of glue logic. At the printed circuit board (PCB) level, glue logic may be implemented with simple “jelly bean” chips (“glue chips”) that contain a few gates all the way to programmable logic devices.

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The use of VHDL to create the sequential logic component of the system

Ref: Digital Fundamentals by Thomas L Floyd

6.8. Real time Applications in day to day life and to Industry

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TRAFFIC SIGNAL CONTROLLER

A traffic signal controller is represented with its combinational logic and sequential logic.

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6.9. Content Beyond Syllabus

FPGA APPLICATION IN EMBEDDED SYSTEMS

The fast growing embedded market is one of most diverse in terms of end application. Embedded includes traditional general purpose ‘embedded CPU’ platforms such as Medical, Robotics, Industrial Control, and Data Acquisition, but can also include Video Surveillance, Automotive, Point-of-Sale, and other more specialized applications. Pericom offers a wide variety of support products for all of these sub segment platforms, ranging from specialized Timing products like processor specific XO and clocks, to Bridge that can connect the latest PCIe based embedded processor families to legacy protocols such as PCI-X, PCI, USB, UART, and more. In fact, Pericom Timing, Switching, and Signal Conditioning products are already used in most embedded platform applications with the most popular embedded processors.

Embedded processors can include CPU chipsets from major CPU vendors, SOC, and FPGA from major vendors which are used across all embedded segments. As an example, the FPGA-Pericom block diagram illustrates the many I/O, power management, and timing functions that Pericom can provide.

​

​

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2. Medical Applications -Digital Stethoscope

Basic digital stethoscopes retain the look and feel of acoustic stethoscopes but improve listening performance. High-end digital stethoscopes offer sophisticated capabilities, such as audio recording and playback, and provide data to visually chart results by connecting to an off-instrument display. This advanced functionality increases the physician’s diagnostic capability. The essential elements of a digital stethoscope are the sound transducer, the audio codec electronics, and the speakers. The sound trans-ducer is the most critical piece in the chain. It determines the diagnostic quality of the digital stethoscope.

The digital stethoscope consists of three different modules, data acquisition, preprocessing, and signal processing, before the listener can appreciate the auscultated sound. The data acquisition module involves a microphone and a piezoelectric sensor. It is responsible for filtering, buffering, and amplification of the auscultated sounds, as well as conversion of the acoustic sound to a digital signal. The preprocessing module filters the digital signal and removes any artifacts. These digital data are then forwarded to the signal-processing module, which will package the information in a higher-order classification and cluster the data for a clinical diagnostic decision.Unlike the acoustic stethoscope, the transducers on a digital stethoscope are of wide variety. One of the transducing methods involves the microphone in the chest piece.16 The sound signals are detected by the stethoscope diaphragm, which is transferred to another diaphragm inside the microphone. This allows for the conversion of a simple and direct acoustic sound to an electrical signal. The signal can then be displayed as a phonocardiogram on an electronic device. However, two diaphragms separated by an air path can result in excessive ambient noise signals and inaccurate electrical signal transfer.

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7.Assessment Schedule

(Proposed Date & Actual Date)

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8. Prescribed Text Books & Reference Books

​

TEXT BOOK:

​

1. M. Morris Mano and Michael D. Ciletti, Digital Design, With an Introduction to the Verilog HDL, VHDL, and System Verilog, 6th Edition, Pearson, 2018.

​

• S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 5th Edition, Oxford University Press, 2018.

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REFERENCES:

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1. A.Anandkumar, Fundamental of digital circuits, 4th Edition, PHI Publication, 2016.

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• William Kleitz, Digital Electronics -A Practical approach to VHDL, Prentice Hall International Inc, 2012.

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• Charles H. Roth, Jr. and Larry L. Kinney, Fundamentals of Logic Design, 7th Edition,Thomson Learning, 2014.

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• Thomas L. Floyd, Digital Fundamentals, 11th Edition, Pearson Education Inc, 2017.

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• John. M Yarbrough, Digital Logic: Applications and Design, 1st Edition, Cengage India, 2006.

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NPTEL LINK: https://nptel.ac.in/courses/108/105/108105132/

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9. Mini Projects Suggestions

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Security Alarm/Burglar Alarm Circuit

​

A burglar alarm system is designed to detect an unauthorized entry into a house or area. Burglar alarm systems can be used in residential buildings, commercial buildings, offices, industries and even in military locations. All you need is just to place this circuit in front of the locker or below the mat so when any unknown person come and walk over the switch, the circuit will trigger and sound of alarm comes. The main benefit of the circuit is that these can be implied in two places at atime as two different switches produces two different sounds.

Circuit Components

• LM358 – 1
• IR Transmitter or IR LED – 1
• Photo Diode – 1
• 10 KΩ – 1
• 150Ω – 1
• 10 KΩ POT – 1
• Buzzer – 1

​

LM358: It is a dual Op Amp IC. It consists of two independent operational amplifiers that can be used separately. It is commonly used in all op amp circuits, transducer amplifiers, active filters, general signal conditioning and DC gain blocks.

IR Transmitter: Infrared or IR is a range of light frequencies that have longer wavelength than visible light. Hence, they are not visible to human eye. An IR transmitter or IR LED is a device that emits infrared light.

Photo Diode: A photo diode is a device that converts light to electrical current. It is basically a PN junction that operates in reverse bias condition. When light falls on the photo diode, a reverse bias current flows in the junction that is proportional to the luminescence of the light.

Buzzer: It is an alarming device that makes a loud sound when current flows through it.

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Security Alarm Circuit

​

​

Circuit Design of Burglar Alarm System

The IR transmitter or IR LED is connected to a current limiting resistor of 150Ω and connected to supply. It is placed at the maximum possible range from photo diode.

The cathode of the photo diode is connected to supply while anode is connected to 10KΩ resistor. Other end of the resistor is connected to ground. The anode terminal

of the photo diode is also connected to pin 5 of LM358 op amp, which is the non- inverting terminal.

Wiper of the 10KΩ POT is connected to the inverting terminal i.e. pin 6 of LM358 while the other two terminals of the POT are connected to Vcc and ground.

Pins 8 and 4 of LM358 are supply pins. They are connected to Vcc and ground respectively.

The output of the op amp is taken at pin 7. One terminal of the buzzer is connected

to pin 7 of LM358 while the other terminal is connected to Vcc.

​

​

Circuit Diagram of Security Alarm

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Security Alarm Circuit

Working of Security Alarm Circuit

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The aim of this project is to implement a simple Burglar Alarm System that can detect an unauthorized entry by a burglar. All the connections are made as per circuit diagram. The working of the circuit is as follows.

LM358 is configured to work as comparator in this project. When the system is powered on, the IR transmitter or IR LED emits infrared light. This light falls on the surface of the photo diode.

As it is connected in reverse bias fashion, when the light falls on it, it conducts and

current flows through it. Since it is connected to the non-inverting terminal (pin 5) of the op amp, output of the op amp comparator will be high. As the buzzer is connected between Vcc and output of op amp, no alarm is made.

When an intruder or a burglar enters the gap between the IR transmitter and photo diode, the light falling on the photo diode is interrupted and it doesn‟t conduct.

As a result, the input at non-inverting terminal (pin 5) is less than the input at inverting terminal (pin 6). Hence, the output of the comparator is low. This will trigger the buzzer and a loud alarm is made.

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Video Link

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https://youtu.be/P3jz1oo-TXk

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USB LED Lamp Circuit

LED Light bulbs are becoming more common and are replacing the CFL Bulbs. With the cost of LED light bulbs becoming lower, people are gradually shifting towards LED Lamps in their homes and offices. In this project, a simple USB LED Lampcircuit is designed. This is an easy to implement DIY circuit that can be used to provide an extra lighting for your laptop or tablet.

​

​

Components Required

• USB Male Connector
• Light Emitting Diodes – 5 X 5mm White LEDs
• Resistors – 100Ω X 5
• Perf Board

Circuit Design of

USB LED Lamp Circuit

The circuit mainly consists of a male USB Connector. USBs can be mainly divided into two standard types – USB of „A‟ type and USB of „B‟ type. These different types of USBs connectors differ in their shapes. Type „A‟ USB can be used with the upstream devices such as USB hub or host. Type „B‟ USB can be used with downstream devices such as printers.

​

The cables will have same number of pins but they differ mechanically. Many versions in USB were released. The first version USB 1.0 and 1.1 had the data rateof 12 Mbps.USB 2.0 has data rate of 480 Mbps.USB 3.0 is expected to have data rateof 4.8 Gbps.

​

USB used here is of type „A‟. It has 4 pins. These pins are VCC, GND, D+, D-. The D+ and D- pins are the data pins. VCC pin outputs the voltage of 5V. The USB LED Lamp with Type „A‟ male USB connector can be simply connected to the USB port ofthe computer.

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USB LED Lamp Circuit

LED is a semiconductor device with two leads. Generally LEDs were used forindicating but now-a-days, LEDs are becoming the main sources of lighting inhomes, offices, streets, automobiles, etc.

An LED is similar to a normal P-N junction diode. The energy emitted is in the form of light when applied with the required voltage, while normal P-N junction diode emits energy in the form of heat.

The color of light emitted depends on the band gap of the semiconductor. The LEDs

used here are normal white LEDs. They have voltage drop of 3.6V. The current required by the LEDs is 40mA.

Initially these LEDs are limited to the red color, later high power LEDs and other colored LEDs such as blue LEDs, white LEDs etc. were developed.

A resistor of 100Ω is connected between the Light Emitting Diode and the USB. This acts as a current limiting resistor. As the LEDs require maximum current of 40mA to glow with full brightness, they are required to protect from current more than this.

So, for that reason, a resistor is to be placed between the LED and the power supply

to limit the amount of current flowing through the LED. The supply voltage coming from the USB is 5V and the current drop at the Light Emitting Diode is 40 milli amperes.

The following formula can be used to calculate the resistor value.

​

R=V/I

​

where, the value of V is 5 volts and the value of I is 40 mA. So,

​

R= 5V/0.04A =125 ohms

But generally, 125 ohm resistor does not exist in real time. Therefore a resistor of 100Ω is used instead of 125Ω.

Though it gives an output current of 50 mA, this can be tolerated by the LED.

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USB LED Lamp Circuit

DIY LED Light Bulb Circuit Diagram

How to Operate USB LED Lamp Circuit?

• Initially connect the circuit as shown in the circuit diagram.
• Now insert the USB to the port of the computer.
• You can observe the lamp glowing
• Now remove the USB from port.
• Now lamp is switched off.

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USB LED Lights Circuit Advantages

• This is simple and inexpensive.
• This is a portable lamp.
• No extra source is required.

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Video Link: https://youtu.be/2n_KU6wgmfM

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Smoke Detector Alarm Circuit

A Smoke Detector is a smoke sensing device that indicates fire. Smoke Detectors are very common in homes, offices, schools and industries. Smoke Detectors are very useful devices as the damage caused by fire accidents is catastrophic. Now a days, smoke detectors and smoke alarms are very cheap as its usage is increasing and cost of manufacturing is decreasing. In this project, a simple Smoke Detector Circuit using simple hardware is implemented.

Components Required

• MQ-2 Sensor
• LM358
• 10KΩ
• 330Ω
• LED
• 0.1µF
• 10KΩ POT

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Circuit Diagram:

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Smoke Detector Alarm Circuit

Working:

Smoke Detectors are amazing devices as they are small, cheap yet very useful. In this project, a simple Smoke Detector Circuit with adjustable sensitivity is implemented.

A Smoke Sensor MQ-2 as the main sensory device. LM358 acts as a comparator in this circuit. The inverting terminal of LM358 is connected to POT so that thesensitivity of the circuit can be adjusted.

The output of LM358 is given to an LED as an indicator although a buzzer can be used

as an alarm. The non-inverting terminal of LM358 is connected with output of smoke sensor.

Initially, when the air is clean, the conductivity between the electrodes is less, as the resistance is in the order of 50KΩ. The inverting terminal input of comparator is higher than the non-inverting terminal input. The indicator LED is OFF.

In the event of fire, when the sensor is filled with smoke, the resistance of the sensor falls to 5KΩ and the conductivity between the electrodes increases.

This provides a higher input at the non-inverting terminal of comparator than the inverting terminal and the output of comparator is high. The alarming LED is turned

ON as an indication of presence of smoke.

Note:

• The heating element in the Smoke Sensor must be preheated before it can sense any smoke or gas.
• The sensor gets hot because of the heating coil and it is advised not to touch the sensor while it is switched on.
• The sensitivity of the circuit to different concentrations of smoke can be adjusted by using the POT.
• The output LED can be replaced with a loud buzzer for effective alarm.

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Video Link: https://circuitdigest.com/electronic-circuits/simple-smoke-detector-alarm-circuit- diagram

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Digital Bank Token Number Display

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Token systems are used to manage queues of people in banks, hospitals and other places. Visitors are allotted serial token numbers and have to wait till there number is called. These no.‟s can be updated by entering the complete no. or by pressing the up/down key in case it's a serially organized count. Here a very simple token system or an up down counter is designed.

Components required :

• 1 x Arduino Uno R3 Board
• 1 x 4 Digit Multiplexed Seven Segment Board
• 1 x 8 Push Button Board
• 1 x Mini Breadboard Optional
• Power Source (Battery with Snapper/DC Adapter) : 9-12V DC
• Tools
• Jumper Wires

Circuit Diagram:

Video Link: https://www.youtube.com/watch?v=quuoFZp0kJs

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Water Level Controller using 8051

​

This system mainly works on a principle that “water conducts electricity”. The four wires which are dipped into the tank will indicate the different water levels. Based on the outputs of these wires, microcontroller displays water level on LCD as well as controls the motor.

Initially when the tank is empty, LCD will display the message LOW and motor runs automatically. When water level reaches to half level, now LCD displays HALF and still motor runs.

When the tank is full, LCD displays FULL and motor automatically stops. Again, the

motor runs when water level in the tank becomes LOW. Components Required for Water Level Controller using 8051 Microcontroller

• AT89C51 Microcontroller (or any 8051 based Microcontroller)
• 8051 Programmer (Programming Board)
• 11.0592 MHz Quartz Crystal
• 2 x 33pF Capacitor
• 2 x 10KΩ Resistor (1/4 Watt), 10µF Capacitor
• Push Button
• 1KΩ x 8 Resistor Pack (for Pull – up)
• 16 x 2 LCD Display, 5V Relay
• 4 x 2N2222 (NPN) Transistors
• DC Motor (for demonstration)
• 10KΩ Potentiometer
• 1N4007 PN Junction Diode
• Programming cable,Connecting wires
• Power Supply
• Keil µVision IDE
• Willar Software (for burning code)
• Proteus (for circuit diagram)

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Water Level Controller using 8051

Water Level Controller using 8051 Microcontroller Circuit Diagram

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Water Level Controller using 8051

​

How to Design Circuit for Water Level Controller using 8051 Microcontroller?

The heart of the Water Level Controller using 8051 Microcontroller project is the AT89C51 Microcontroller. The water level probes are connected to the P0.0, P0.1 and P0.2 through the transistors (they are connected to the base of the transistors through corresponding current limiting resistors). P0.0 for LOW level, P0.1 for HALF Level and P0.2 for HIGH Level.

The Collector terminals of the Transistors are connected to VCC and the Emitter terminals are connected to PORT0 terminals (P0.0, P0.1 and P0.2).

PORT1 of the microcontroller is connected to the data pins of LCD and the control pins RS, RW and EN of the LCD Display are connected to the P3.6, GND and P3.7 respectively.

For demonstration purpose, a simple DC Motor Pump is used. It is connected to the

Relay and the input to the relay is fed from P0.7 through a transistor.

Algorithm for Water Level Controller Circuit

• First configure the controller pins P0.0, P0.1 and P0.2 as inputs and P0.7 as output.
• Now, initialize the LCD.
• Continuously check the water level input pins P0.0, P0.1 and P0.2.
• If all the pins are low, then display tank as “EMPTY” on the LCD and make P0.7 pin HIGH to run the motor automatically.
• If the level is low i.e. if P0.0 is HIGH, display the water level as “LOW” and

continue to run the motor.

• A HIGH pulse on the pin P0.1 indicates that water has reached half level. So, display the same thing on LCD and run the motor normally.
• If P0.2 is HIGH, then the water level in the tank is FULL.
• Now, make the P0.7 pin as LOW to turn off the motor automatically.

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Water Level Controller using 8051

​

How to Operate Water Level Controller Circuit using 8051 Microcontroller?

1. Initially, write the program for Water Level Controller in Keil µVision IDE and generate the .hex file.
2. Burn the program (.hex file) to the microcontroller using external programmer and Willar Software.
3. Now give the connections as per the circuit diagram.
4. While giving the connections, make sure that there is no common connection between AC and DC supplies (if you are using an AC Motor)
5. Place the 4 water level indicating wires into the small tank (3 probes for three

different levels and fourth one for common supply)

6. Switch on the supply. Now, the motor will run automatically as there is no water in the tank. (It will turn on even if the water level is LOW).
7. Now pour the water, when it reaches LOW level, then LCD displays LOW.
8. For middle level, it will display as HALF on the LCD.
9. Still if you pour the water, then the water level reaches full and the LCD displays FULL and also the motor is turned OFF automatically.
10. Switch off the motor supply and board supply.

Video Link: https://www.youtube.com/watch?time_continue=112&v=tYwQTTG- GDg&feature=emb_logo

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MINI PROJECT – II (Contd.)

1. The outputs of comparators are given as inputs to the priority encoder and the corresponding binary outputs are generated. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs. The output of the first comparator will be higher priority input compared to other bits.

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INPUT & OUTPUT

CIRCUIT DIAGRAM

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9. Mini-projects suggestions (Cont.)

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1. FPGA Based Robotic Arm Controller

A robotic arm is a type normally programmable mechanical arm, which can be used to pick and place various objects in the industries from one place to another place. It may be the sum total of the mechanism or may be part of a more complex robot. The parts of these manipulators or arms are interconnected through articulated joints that allow both a rotational movement. The FPGA based project is implemented using Spartan3an Project Kit and Robotic ARM kit.

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2. Tic-Tac-Toe game using FPGA:

This design accomplished Tic-Tac-Toe game on Spartan3 FPGA Image Processing kit in VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly, designing the algorithm and programming it in VHDL. Thirdly, synthesizing it in Xilinx Synthesis tool and then implementing it in Xilinx ISE developing suite. Finally download it onto FPGA to run it. This design allows two players to play Tic-Tac-Toe game on the experiment board. The user plays the game from the keyboard. He uses the arrows to move a square on a 3x3 grid on the VGA display. The Xs and 0s are placed by pressing the space bar. The user can move a switch to choose the game mode. He can play against another player or alone against the design. When playing alone, after a X is placed the position of the 0 is returned but not yet shown on the display. Only after another key is pressed the 0 appears on the grid. When the game ends (X or 0 wins or draw game) the marks are automatically erased from the grid and the score is incremented on the seven-segment LED display.

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3. High Precision Digital Voltmeter :

The digital voltmeter design uses a microcontroller which is said to be highly efficient in handling the data carrier operation in terms of being faster, error-free and accurate. Rather than using the absolute analog ways of finding out the voltages, the digital voltmeter provides much more precise and accurate values of voltages in a given circuit in the range of the voltmeter.

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4. Digital Soil Moisture Tester

This digital soil moisture tester project is used to check whether the soil is wet or dry, and also to check the wetness or dryness of cotton (woven and woolen) fabrics. In this project, the tester uses a number of LEDs driven by a display driver IC LM3915. When the two test probes are inserted in the soil, the display shows the relative magnitude of conductance between the two test probes. And, also measures the dryness or wetness of the soil which is indicated by sequential lighting of LED1 through LED9.

5. Robot for Detecting Table Edge

This project is used to design a robot using logic gates. This robot is mainly used to detect the edge of the table because when this robot moves in a straight line, it stops once it detects an edge of the table. To overcome this, this robot is very useful in detecting the table edge. Once it detects, it automatically changes its direction and moves in the forward direction.

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9. Mini-projects suggestions (Cont.)

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6. Gaming control

Many game shows use a circuit to determine which of the contestants ring in first. Design a circuit to determine which of two contestants rings in first. It has two inputs S1 and S0 which are connected to the contestants' buttons. The circuit has two outputs Z1 and Z0 which are connected to LED's to indicate which contestant rang in first. There is also a reset button that is used by the game show host to asynchronously reset the flip-flops to the initial state before each question. If contestant 0 rings in first, the circuit turns on LED 0. Once LED 0 is on, the circuit leaves it on regardless of the inputs until the circuit is asynchronously reset by the game show host. If contestant 1 rings in first, the circuit turns on LED 1 and leaves it on until the circuit is reset. If there is a tie, both LED's are turned on. The circuit requires four states: reset, contestant 0 wins, contestant 1 wins, and tie. One way to map the states is to use state 00 for reset, state 01 for contestant 0 wins, state 10 for contestant 1 wins, and state 11 for a tie. With this mapping, the outputs are equal to the current state, which simplifies the output equations.

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7. Traffic light controller

Design a simplified traffic-light controller that switches traffic lights on a crossing where a north-south (NS) street intersects an east-west (EW) street. The input to the controller is the WALK button pushed by pedestrians who want to cross the street. The outputs are two signals NS and EW that control the traffic lights in the Ns and EW directions. When NS or EW are 0, the red light is on, and when they are 1, the green light is on. When there are no pedestrians, NS=0, EW=1 for a minute, follow by NS=1 and EW=0 for 1 minutes, and so on, when WALK button is pushed, Ns and EW both become 0 for a minute when the present minute expires. After that the NS and EW signals continue alerting. For this traffic-light controller: a) Develop a state diagram. (Hint: can be done using 3 states) b) Draw the state transition table. c) Encode the states using minimum number of bits. d) Derive the logic schematic for a sequential circuit which implements the state transition table.

8. Bidirectional Visitor Counter

Display the number of students in the class. Whenever a student enters the class, an upcounter is activated and the display increases by 1. Whenever a student leaves the class, a down counter is activated and the display decreases by 1.

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9. Count the number of cars in a parking lot

Display the number of cars in the parking lot. Whenever a car enters the parking lot, an upcounter is activated and the display increases by 1. Whenever a car leaves the parking lot, a down counter is activated and the display decreases by 1.

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5. Automatic Washroom Light Switch

(https://www.electronicshub.org/automatic-washroom-light-switch/)

The reed switch is fixed to the wall near the door while the magnet is fixed to the door. This means that the reed switch will always be in closed state as the door is closed when the washroom is not in use (which is assumed as starting point) and the magnet will be near the switch. When the door is opened and then closed the door, this action will make the switch open (when the door is opened first) and close (when you close the door). As a result, the output of the Op-amp goes HIGH (when open the door) and then goes LOW (when close the door). This in turn will cause the counter to produce a HIGH output at its Pin 2. Since Pin 2 of CD4017 is connected to the relay, the light will be turned ON. While coming out, the door is once again opened and closed. This action will once again cause the same action i.e. switch will open and close and output of Op-Amp will become HIGH and then LOW. But, since the Pin 4 of CD4017 is connected to the Reset pin, all the outputs will become LOW and hence the relay will be turned OFF, which in turn switches off the light.

6. Dancing LEDs

A group of 10 LEDs is connected to a 10 bit shift register. Whichever LED has to glow, then send 1 for others 0. Thus by sending different combinations of 1’s and 0’s the LEDs are made to glow in different fashion making them to dance.

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7. Digital Alarm

The clock is given in such a way that the 4 bit counter increases its count after 1 sec. After the counter counts 10, the buzzer will give alarm sound. Thus it produces a 10 sec alarm

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8. Design a traffic light

A traffic light is installed at a junction of a railroad and a road. The light is controlled by two switches in the rails placed 1 mile apart on either side of the junction. A switch is turned on when the train is over it and is turned off otherwise. The traffic light changes from green (logic 0) to red (logic 1) when the beginning of the train is 1 mile from the junction. The light changes back to green when the end of the train is 1 mile away from the junction. Assume that the length of the train is less then 2 miles. Obtain a primitive flow table for the circuit. Show that the flow table can be reduced to four rows. With further procedures implement the same.

9. 12-Hour Clock

Digital clocks are usually set up to start at 12:00, and they count 12:01, 12:02, 12:03, 12:04, 12:05, 12:06, 12:07, 12:08, 12:09, 12:10, and eventually the clock gets to 12:58, 12:59, 1:00, and so on. The one's place of the minutes (the right-most digit) counts 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and then repeats, and a circuit that counts in this way is called a mod-10 counter. The ten's place of the minutes (second digit from the right) counts 0, 1, 2, 3, 4, 5, and then repeats, which is called a mod-6 counter. The hour counter counts 12, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and repeats. The output from each counter is a binary coded decimal (BCD) number that represents one of the digits in the time, and BCD-to-Seven segment decoders are used to drive the seven segment displays

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10. Contents beyond the Syllabus ( COE related Value added courses)

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VHDL Coding for FPGAs – Contents for Embedded Systems CoE.

DIGITAL LOGIC DESIGN DESIGN FLOW

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DATA TYPES

LOGIC GATES IN VHDL TESTBENCH GENERATION

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XILINX: I/O ASSIGNMENT

USE OF std_logic_vector DESIGN FLOW

Design Entry: The logic circuit is specified using a Hardware Description Language (e.g., VHDL, Verilog).

Functional Simulation: Also called behavioural simulation. Here, we will only verify the logical operation of the circuit. Stimuli is provided to the logic circuit, so we can verify the outputs behave as we expect.

​

Physical Mapping: The inputs/outputs of our logic circuit are mapped to specific

pins of the FPGA.

Timing Simulation: It simulates the circuit considering its timing behavior (delays between inputs and outputs)

​

Implementation: A configuration file (‘bitstream’ file) is generated and then

downloaded onto the FPGA

​

https://www.secs.oakland.edu/~llamocca/VHDLforFPGAs.html

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