Are you aspiring to be a "Design Verification Engineer"? Do you want to catch up with the latest in the field of VLSI Design-Verification? Want to know what's coming in IEEE 1800.2 UVM? Join us for this FREE event.
"Straight from horse's mouth "- aptly describes this edition of our DVTalk scheduled for Apr-24, 2018 at VerifWorks Bangalore office! Come and learn what is new with IEEE UVM, UVM for RTL Designers with Go2UVM and much more, all for free!
9.00 - 9.30 - Welcome, registration 9.30 - 10.00 - Introduction, Agenda10.00 - 10.45 - UVM for RTL Designers10.45 - 11.00 - Tea and snacks break11.00 - 13.00 - IEEE 1800.2 UVM - What’s new? - Straight from the horse’s mouth!
13.00 - 14.00 - Lunch Break14.00 - 15.00 - VLSI career - introduction and opportunities 15.00 - 16.00 - SystemVerilog Assertions - practical applications