Logic Design (DEC) Pre-Lab Quiz 8 & 9 Combined
This is a Continuous Internal Evaluation component of the Laboratory course.
Deadline: 19th October 2016 at 10 AM.

Problem Statement for Synchronous Counter experiment :
9 a) Design MOD-N counter using IC 7476 in T-FLIP FLOP(T-FF) configuration.
9 b) Verify IC 74193 and observe UP/DOWN counter using the datasheet.

All the students are informed to come to the lab with the observation book write up including logic diagrams , Truth Tables , IC pin configuration etc.. relevant to the above experiment

Also, bring THREE assessment sheets for the assessment of Quizzes on FlipFlops(Quiz 7), Asynchronous Counters(Quiz 8) and Synchronous Counters(Quiz 9).

Download material of Expt. 9 from here. https://docs.google.com/document/d/1HQt6wT_Qe_D7wKg5s0eBMcFbkXmHQMpGK3f3XP2tqgQ/edit?usp=sharing

IC 74192 is *
1 point
Enter your Division *
Enter your email ID *
IC 74193 is *
1 point
In Synchronous Counter, *
1 point
Which FF is used for synchronous counters? *
1 point
"State" in a counter means *
1 point
Counter is counting from 00000 to 11111. Clock frequency is 32KHz. What is the frequency of output signal? *
1 point
Enter your Name *
MOD 10 counter can be designed with the help of *
1 point
Counters are used in 555 timer *
1 point
MOD Number means *
1 point
Only the first Flip-Flop of a ripple counter is controlled by a clock, the counter is *
1 point
Enter your USN *
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