Session 4 - Advanced Accelerators and Digital Design Techniques - April 15, 10:30 am - 12:05 pm
4-1 OPTIMO: A 65nm 270MHz 143.2mW Programmable Spatial-Array-Processor with a Hierarchical Multi-cast On-Chip Network for Solving Distributed Optimizations (M.Chang, L.Lin, J.Romberg, A.raychowhury)
Presentation Quality
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Technical Quality
Best
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4-2 A 2048-Neuron Spiking Neural Network Accelerator with Neuro-Inspired Pruning and Asynchronous Network on Chip in 40nm CMOS (Sung-Gun Cho, Edith Beigne, Zhengya Zhang)
Presentation Quality
Best
Technical Quality
Best
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4-3 A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS
Presentation Quality
Best
Technical Quality
Best
4-4 A 0.5 V 2.5 uW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM retention in 55 nm Deeply-Depleted Channel CMOS (M. Pons, C. Muller, D. Ruffieux, J. Nagel, S. Emery, A. Burg, S. Tanashi, Y. Tanaka, A. Takeuchi)
Presentation Quality
Best
Technical Quality
Best
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