Self-Assessment Quiz
The learning objectives of this self-assessment are to help you validate your understanding of basic Verilog syntax, signal values in Verilog, and instantiating modules in Verilog.

The quiz is intended to be a formative assessment to guide your learning. The automated feedback you get at the end of the quiz will point you to the sections of the material you should focus on for better grasp of the concept related to each question.
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The basic unit of organization in a Verilog design is a *
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The signals `inSignal` and `outSignal` are part of what construct of the following Verilog module? *
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The signals `inSignal` and `outSignal` are part of what construct of the following Verilog module? *
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In the following snippet of Verilog, what is the name of the module the snippet is instantiating? *
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In the following snippet of Verilog, what is the name of the instance the snippet is instantiating? *
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In the following snippet of Verilog, what are the input signals of the instance the snippet is instantiating? *
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In the following snippet of Verilog, what are the output signals of the instance the snippet is instantiating? *
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Which of the following value specifications are incorrect? *
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What is the radix of the value 8'hff?
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What does the symbol 'X' in a value in Verilog stand for? *
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What does the symbol '?' in a value in Verilog stand for? *
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What does the symbol 'Z' in a value in Verilog stand for? *
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