Telangana Academy for Skill and Knowledge (TASK) & C-DAC Hyderabad - Faculty Updation Programme (FUP) on "On Digital VLSI System Design using Verilog HDL " during 12th

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Telangana Academy for Skill and Knowledge (TASK) & C-DAC Hyderabad - Faculty Updation Programme (FUP) on "On Digital VLSI System Design using Verilog HDL " during 12th - 16th June 2017

Please use this form to inform us if you will be able to attend the Faculty Updation Program - FUP "Digital VLSI System Design using Verilog HDL" to be held from 12th June to 16th June 2017 at Marri Laxman Reddy Institute of Technology and Management, Hyderabad.

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Please write your name: *

Please write your designation: *

Please select the Faculty Updation Program (FUP) *

VLSI System Design

Please mention the name of your institution/college: *

Please mention the name of your department *

Please give your e-mail id : *

Please give your mobile number : *

Please provide your city / district : *

Kindly confirm whether you will be able to attend the FUP Digital VLSI System Design using Verilog HDL to be held from 12th June to 16th June 2017. *

Venue: Marri Laxman Reddy Institute of Technology and Management,Dundigal, Hyderabad, Telangana 500043

YES

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