SDAccel Design Contest
Data center operators constantly seek more server performance. Currently they develop applications with easy-to-program multicore CPUs and GPUs but CPU performance/watt is hitting the wall and GPU performance/watt is hitting the wall as well. Designers working on high-volume data-center applications want GPU ease-of-programming but with hardware that will give them low power consumption, high throughput, and the lowest possible latency. However, there’s a significant problem with scalability of multicore-CPU and GPU accelerators: developers would like to target simple full height plug-in PCIe boards to use as application accelerators in data center servers.
FPGAs provide the heart of what’s needed for power-efficient hardware application acceleration on one chip while providing solutions that are below the 25W per board targets.
The SDAccel development environment for OpenCL, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx family, combines the industry's first architecturally optimising compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

At NECSTLab we are organising the first SDAccel Design Contest, which will take place during the second semester.

During this period of time, participants will have the chance to attend some special tutoring sessions on SDAccel.
Classes Timetable:
11th of Jan 4pm-8pm: Vivado and Vivado HLS
18th of Jan 4pm-8pm: Vivado and Vivado HLS
25th of Jan 4pm-8pm: Vivado and Vivado HLS
1st of February 4 pm-8pm: SDAccel
8th of February 4 pm-8pm: SDAccel
15th of February 4 pm-8pm: SDAccel
22nd of February 4pm-8pm: SDAccel

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