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Designs continue to grow in size and complexity and it is no longer feasible to create separate tests in UVM, C or any other environment at each stage of your verification as you go from block- to system-level.
Today’s verification entails running on different platforms, from virtual prototyping to simulation, emulation, FPGA prototyping and even silicon, each of which requires its own environment. The key to productivity is to reuse test intent seamlessly throughout the process.
Matthew Ballance, Product Engineer and Portable Stimulus Technologist, from Mentor who are leading participants of the Accellera Portable Stimulus Working Group will provide a detailed look at how the new standard allows you to specify your verification intent at an abstract level to make you more productive in creating scenarios.
You’ll also see how Portable Stimulus can be used on real-life examples to generate coverage-driven tests in multiple output formats, including UVM and C.