Topic 06 Material Pre-Assessment
Before beginning the material for this chapter, evaluate your prior familiarity with the material.

The pre-assesment is intended to be a formative assessment to guide your learning. The automated feedback you get at the end of the assessment will point you to the sections of the material you should focus on for better grasp of the concept related to each intended learning outcome.
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Read and write hardware descriptions in the Verilog hardware description language. *
The basics of the Verilog syntax (modules, wires, types, `include, etc.) *
Design hardware in Verilog at transistor, gate / hard IP, or behavioral level. *
Use tools like Yosys, Iverilog, Vvp, and GTKWave to simulate your Verilog design *
Implement and test designs (D-type flip flop and 1Hz LED blinker) in multiple Verilog design styles. *
Identify some different methods to use circuits to achieve computation. *
Enumerate differences between a programmable processor and programmable logic. *
Enumerate the differences between PALs, PLAs/CPLDs, and FPGAs. *
Which of the learning outcomes for this chapter do you already feel confident with? *
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Which of the learning outcomes for this chapter do you feel least confident with? *
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