Registration Hours

Date

Time

Location

December 7th,2008

20:00~22:00

Hotel Lobby (1F)

December 8th,2008

7:00~17:20

Conference Room Hallway (3F)

December 9th,2008

7:00~17:20

Conference Room Hallway (3F)

December 10th,2008

8:00~12:00

Conference Room Hallway (3F)

 

 

Sunday Program

 

Date

Time

Event

Sunday

12/07/2008’

 

12:00~12:30

Bus Drive to National Taiwan University

12:30~13:00

Workshop Registration and Lunch

(Registration is free and open to all)

13:00~13:15

Welcome Remarks

Brent Nelson, Brigham Young University

13:15~14:30

Invited Talks

“A Broader Look at FPGA Design Productivity”

Peter Athanas, Virginia Tech, USA

13:40~14:05

Invited Talks

“Architectural Support for Productivity”

Philip leong, Chinese University of Hong Kong

14:05~14:30

Invited Talks

“Bringing Modern Modeling Abstractions into Configurable Computing”

David Andrews, University of Arkansas, USA

14:30~14:45

Coffee Break

14:45~15:45

Group Session

Panel discussion and group interaction activity

15:45~16:00

Wrap Up

16:00~18:00

City Tour By Bus

18:00~18:30

Bus Drive to Hotel

Regular Program

 

Date

Time

Event

Monday

12/08/2008

8:00~8:30

Opening Remarks and Award Presentation

Wai-Kai Mak, National Tsing Hua University, Taiwan

Tarek El-Ghazawi, George Washington University, U.S.A

Yao-Wen Chang, National Taiwan University, Taiwan

8:30~9:30

Keynote Talk

Re-Visiting the challenges of Programmable Concurrent Architectures

Patrick Lysaght, Xilinx

9:30~10:15

Poster Session 1 – Coffee Break

Chair: Iris Hui-Ru Jiang

10:15~11:55

Session1: Tools I 

Chair:  Guy Lemieux

Co-optimisation of Datapath and Memory in Outer Loop Pipelining

Kieron Turkington, George A. Constantinides, Kostantinos Masselos and Peter Y.K. Cheung

Wave-Pipelined Signalling for On-FPGA

Communication

Terrence Mak, Pete Sedcole, Peter Cheung and Wayne Luk

Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver

Wei Zhang, Vaughn Betz and Jonathan Rose

A System-Level Stochastic Circuit Generator for FPGA Architecture Evaluation

Cindy Mark, Ava Shui and Steve Wilton

11:55~13:00

Lunch

13:00~14:40

Session2: Arithmetic

Chair: Ali Akoglu

An FPGA-specific Approach to Floating-Point

Accumulation and Sum-of-Products

Florent de Dinechin, Bogdan Pasca, Octavian Cret and Radu Tudoran

Optimizing Residue Arithmetic on FPGAs

Haohuan Fu, Oskar Mencer and Wayne Luk

Reconfigurable Array for Transcendental Functions Calculation

Mihai Sima, Michael McGuire and Scott Miller

Optimizing Coarse-Grained Units In Floating Point Hybrid FPGA

Chi Wai Yu, Alastair M. Smith, Philip H.W. Leong, Wayne Luk and Steven J.E. Wilton

14:40~15:15

Poster Session 2 – Coffee Break

Chair: Hung-Ming Chen

15:15~17:20

Session3: Applications I

Chair: Lesley Shannon

Hardware Acceleration of Approximate Palindromes Searching

Tomas Martinek and Matej Lexa

PERG: A Scalable FPGA-based Pattern-matching Engine with Consolidated Bloomier Filters

Johnny Ho and Guy Lemieux

Design and Implementation of a High Performance Financial Monte-Carlo Simulation Engine on an FPGA Supercomputer

Xiang Tian and Khaled Benkrid

Estimation of sample mean and variance for Monte-Carlo simulations

David B. Thomas and Wayne Luk

Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain

Oliver Sander, Matthias Traub, Michael Huebner and Juergen Becker

Date

Time

Event

Tuesday

12/09/2008

8:00~9:30

Invited Talks

FPGA Timing, Power, Signal Integrity and Other Challenges at 65 and 45 nm

Paul Leventis, Altera

FPGA Design Productivity – A Discussion of the State of the Art and A Research Agenda

Brent Nelson, Brigham Young University

9:30~10:15

Poster Session 3 – Coffee Break

Chair: Juinn-Dar Huang

10:15~11:55

Session 4: Tools II 

Chair: Brent Nelson

A transition probability based delay measurement method for arbitrary circuits on FPGAs

Justin S. J. Wong, Pete Sedcole and Peter Y. K. Cheung

A Profiler for a Heterogeneous Multi-Core

Multi-FPGA System

Daniel Nunes, Manuel Saldaña and Paul Chow

Defining Neighborhood Relations for Fast Spatial-Temporal Partitioning of Applications on Reconfigurable Architectures

Joon E. Sim, Tulika Mitra and Weng Fai Wong

Accelerating Hardware Simulation: Testbench

Code Emulation

Iakovos Mavroidis and Ioannis Papaefstathiou

11:55~13:00

Lunch

13:00~14:40

Session 5: Architectures I

Chair: Chia-Lin Yang

Exploring the optimal size for multicasting

configuration data of Dynamically Reconfigurable Processors

Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng and Hideharu Amano

A Scalable Reconfiguration Mechanism for

Fast Dynamic Reconfiguration

Heiko Hinkelmann, Peter Zipf and Manfred Glesner

Memory Security Management for Reconfigurable Embedded Systems

Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan and Kris Gaj

ACS: an Addressless Configuration Support for Efficient Partial Reconfigurations

Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel and Usama Malik

14:40~15:15

Poster Session 4 – Coffee Break

Chair: Chun-Yao Wang

15:15~17:20

Session 6: Application II 

Chair: Philip Leong

A Self-Adaptive Pattern Recognition Hardware with On-chip Partial Reconfiguration

Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette and Jim Torresen

An Run-Length Based Connected Component

Algorithm for FPGA Implementation

Kofi Appiah, Andrew Hunter, Patrick Dickinson and Jonathan Owens

Optimized single pass connected components analysis

Ni Ma, Donald Bailey and Christopher Johnston

Exploiting Memory Hierarchy for a Computational Fluid Dynamics Accelerator on FPGAs

Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita and Hideharu Amano

FPGA Implementation and Analysis of Random Delay Insertion Countermeasure against DPA 

Yingxi Lu, Maire O'Neill (nee McLoone) and John McCanny

 

18:00~18:30

Transportation to Taipei 101

18:30~20:30

Banquet is at Shinyeh Restaurant on the 85/F of Taipei 101

Date

Time

Event

2008/12/10

Wednesday

8:30~10:00

Invited Panel: Research Directions of Reconfigurable Computing

(Organizer: Wayne Luk, Imperial College)

 

Hideharu Amano, Keio University

Tughrul Arslan, University of Edinburgh

Guy Gogniat, European University of Brittany

Ryan Kastner, University of California, San Diego

 

10:00~10:15

Coffee Break

10:15~12:20

Session 7: Architecture II  

Chair: Hideharu Amano

Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs

Moritz Schmid, Daniel Ziener and Juergen Teich

Modelling and Compensating for Clock Skew

Variability in FPGAs

Pete Sedcole, Justin Wong and Peter Cheung

Kernel Sharing on Reconfigurable Multiprocessor Systems

Philip Garcia and Katherine Compton

Evaluating the Impact of Customized Instruction Set on Coarse Grained Reconfigurable Arrays

Julio OliveiraFilho and Wolfgang Rosenstiel

Balanced Allocation of Compute Time in

Hardware-Accelerated Systems

Wenyin Fu and Katherine Compton

 

12:20~12:30

Closing Remark

Wai-Kei Mak, National Tsing Hua University Taiwan

 

          

Poster Session 1 – Monday 8th December

Chair: Iris Hui-Ru Jiang

Title

Presenter

Processor Customization for Wearable Bio-monitoring Platforms

Huynh Phung Huynh and Tulika Mitra

An implementation of a watershed algorithm based on connected components on FPGA

Dang Ba Khac Trieu and Tsutomu Maruyama

The Replacement of the Fixed Multi-PR Region Model with a Flexible, Dynamic PR Domain for DPR Systems

 

Edward Chen, Dorian Sabaz, William A. Gruver and Lesley Shannon

Exploring Hard and Soft Networks-on-Chip for FPGAs

 

Rosemary Francis and Simon Moore

An Approach for Downscaling Images for Real-time Pattern Detection

Yoshifumi Tanida and Tsutomu Maruyama

Dynamically Programmable Reed Solomon Processor with Embedded Galois Field Multiplier

Ahmed O. El-Rayis, Xin Zhao, Ahmet T Erdogan and Tughrul Arslan

Evaluation of Compact High-Throughput Reconfigurable Architecture Based on Bit-Serial Computation

Kazuya Tanigawa and Tetsuo Hironaka

Synthesis of Efficiently Reconfigurable Datapaths for Reconfigurable Computing

Markus Rullmann and Renate Merker

Poster Session 2 – Monday 8th December

Chair: Hung-Ming Chen

Title

Presenter

Makespan Minimization in Automatic Synthesis of Multiprocessor Systems from Parallel Programs

Harold Ishebabi, Philipp Mahr and Christophe Bobda

A New Coarse-Grained FPGA Architecture Exploration Environment

Husain Parvez, Zied Marrakchi, Umer Farooq and Habib Mehrez

An analogue reconfiguration period adjustment technique for optically reconfigurable gate arrays

Takayuki Mabuchi and Minoru Watanabe

An 11,424 gate dynamic optically reconfigurable gate array VLSI

 

Mao Nakajima and Minoru Watanabe

A Systolic Regular Expression Pattern Matching Engine and its Application to Network Intrusion Detection

 

Yosuke Kawanaka, Shin'ichi Wakabayashi and Shinobu Nagayama

Evaluating Power and Energy Consumption of FPGA-based Custom Computing Machines for Scientific Floating-Point Computation

 

Kentaro Sano, Takeshi Nishikawa, Takayuki Aoki and Satoru Yamamoto

A Dynamically Reconfigurable Field Programmable Gate Array Hardware Foundation for Security Applications

 

Samuel Stone, Roy Porter, Yong Kim and Jason Paul

Quad-Level Bit-Stream Signal Processing On FPGAs

 

Chiu-Wa Ng, Ngai Wong, Hayden Kwok-Hay So and Tung-Sang Ng

A Low Power Reconfigurable Heterogeneous Architecture for A Mobile SDR System

Zong Wang and Tughrul Arslan

Poster Session 3 – Tuesday 9th December

Chair: Juinn-Dar Huang

Title

Presenter

High Level Quantitative Interconnect Estimation for Early Design Space Exploration

 

Roel Meeuws, Kamana Sigdel, Yana Yankova and Koen Bertels

Unrolling-based loop mapping and scheduling

 

Yuet Ming Lam, Wayne Luk, Jose Gabriel F. Coutinho and Philip Heng Wai Leong

Concurrent Timing Based And Routability Driven Depopulation Technique For FPGA Packing

Audip Pandit, Lakshmi Easwaran and Ali Akoglu

Leakage Power Reduction for Coarse-Grained Dynamically Reconfigurable Processor Arrays with Fine-Grained Power Gating Technique

Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami and Hideharu Amano

Extending Booth Algorithm to Multiplications of Three Numbers on the FPGA

Yosi Ben Asher and Esti Stein

A Scalable FPGA Architecture for Non-Linear SVM Training

 

Markos Papadonikolakis and Christos-Savvas Bouganis

A Low Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System

Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi and Masahiko Yoshimoto

Creating Digital Fingerprints on Commercial Field Programmable Gate Arrays

James Crouch, Hiren Patel, Yong Kim, J. Todd McDonald and Tony Kim

 

 

Poster Session 4 – Tuesday 9th December

Chair: Chun-Yao Wang

Title

Presenter

An Area-Efficient FPGA Realisation of a Codebook-Based Image Compression Method

 

Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru and Manfred Glesner

A Floating-Point Solver for Band Structured Linear Equations

 

Antonio Roldao, Eric Kerrigan and George Constantinides

FPGA Elliptic Curve Cryptographic Processor over GF(2^m) with Coordinate Collapsing

 

Samuel Antão, Ricardo Chaves and Leonel Sousa

An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs

Wayne Chen and Lesley Shannon

Delay Evaluation of 90nm CMOS Multi-Context FPGA with Shift-Register-type Temporal Communication Module for Large-Scale Circuit Emulation

Naoto Miyamoto and Tadahiro Ohmi

 

ρ-VEX: A Reconfigurable and Extensible Softcore VLIW Processor

 

Stephan Wong, Thijs van As and Geoffrey Brown

Automatic Generation of Decomposition based Matrix Inversion Architectures

Ali Irturk, Bridget Benson and Ryan Kastner

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI

Shinichi Katou and Minoru Watanabe

Real-Time FPGA Architecture of Extended Linear Convolution for Digital Image Scaling

Chung-chi Lin