Graduate Qualifying Exam

Architecture Portion

Study Materials

Computer Science Department

Georgetown University

Topic Coverage

Basic computer design [See (1.), Chapter 4, Appendix C]

   -- devices, logic design, and finite-state machines

   -- simple multi-cycle processor components and organization

   -- simple instruction set architecture

   -- language layers and translation

   -- OS layering, hardware/software interfaces, entering and exiting the kernel

   -- I/O, interrupts, interconnects and busses, DMA, bandwidths and capacities

Technology trends and their effects on computer architecture

   -- device technology trends and Moore’s Law

   -- fixed costs, customization, configurability, and profitability

   -- hierarchical design, abstraction, and standardized interfaces

   -- sales volume, yield, uniformity, and generality

   -- Amdahl’s Law and the common case

   -- cost versus performance/return

   -- energy, power, and infrastructure as systemic limitations

   -- speedup and the three parallelism principles: pipelining, interleaving, and multiplicity

Performance evaluation

   -- data dependency graphs, data flow graphs, and tagged dataflow execution

   -- the processor performance equation

   --  program traces, instruction mixes, benchmark suites

   --  performance summaries and comparing means

Caches

   -- bandwidth and latency trends in SRAM, DRAM, and processors

   -- memory organization, heirarchies, and power consumption

   -- general access maps and associative lookup

   -- the cache performance equation

   -- cache organization alternatives, pipelined and overlapped operations

   -- cache element access and critical paths

   -- write and replacement methods and penalty and bandwidth implications

   -- program access patterns and performance effects

   -- miss rates and block and cache sizes, associativity, and multi-level caches

   -- split caches, prefetching

Virtual Memory (VM)

   -- page size, fragmentation, access penalty, miss rates, and program performance

   -- address mapping, sharing, and protection

   -- I/O buffers and cache coherence

   -- translation caching (TLB) and miss rates

   -- page table sizes, multi-level and inverted tables

   -- data and instruction cache interaction

   -- page replacement policies

   -- virtual versus physical caches

Instruction-level Parallelism

   -- simple processor pipelining, data and control hazards, pipelined decode and control

   -- tracking data dependencies, forwarding, stalling, and nullifying

   -- branch prediction and speculation

   -- out-of-order execution, multiple issue, concurrent pipelined units

   -- loop unrolling, software pipelining, dynamic scheduling

   -- instruction issue, reservation stations, instruction commit, data tagging and matching

   -- coarse-grained, fine-grained, and simultaneous multi-threading

   -- exception handling, state, precise exceptions, pipeline exception control

Thread-level Parallelism

   -- shared memory architectures, private data, asymmetric access

   -- cache coherence, snooping and directories

   -- relaxed and sequential consistency, program semantics

Data Parallelism

   -- VLIW, EPIC and vectorized ALUs, predicated execution

   -- vector operations, multiple lanes, memory banking

   -- SIMD versus MIMD versus SIMT, thread scheduling

   -- vector processor versus GPU organization

Reading List

[1.] Patterson and Hennessy, 2011. Computer Organization and Design: The Hardware/Software Interface, 4e, Revised. Morgan-Kauffman. ISBN: 978-0-12-374750-1

[2.] Hennessy and Patterson, 2011. Computer Architecture: A Quantitative Approach, 5e. Morgan-Kauffman. ISBN 978-0-12-383872-8