PDC OBJECTIVE QUESTIONS
UNIT-I
Multiple Choice Questions :
1.High pass RC circuits produces position and Negative spikes in the following condition [ ]
a) RC << T b) RC >> T c) RC = T d) RC > T
2. Relation between percentage tilt and lowest 3dB frequency is [ ]
a) X 100 % b) π f. f X 100 % c) X 100 % d) X 100 %
3.A RC differentiator converts triangular wave into [ ]
a) spikes b) square wave c) sinusoidal d) ramp
4.In case of parallel RLC circuits, out put is critically damped for the following condition [ ]
a) K = 1 b) K = 0 c) K > 1 d) K < 1
5.for perfectly compensated attenuator, the condition [ ]
a) R1 C2 = R2 C1 b) R1 / C1 = R2 / C2 c) R1 / C1 = R2 / C2 d) C1 C2 = R1 R2
6. Percentage tilt of a HPRC circuit is_ [ ]
a)p=T/RC*50% b)p=T/2RC*100% c)p=T/2RC*25% d)T/4RC*100%
7. Relation between risetime & timeconstant of LPRC circuit is_ [ ]
a)tr=1.1RC b) tr=2.2RC c) tr=4RC d) tr=RC/2.2
8. The waveform of pulse voltage transmitted through LPRC circuit can be preserved provided_ [ ] a) tr=2.2tp b) tr=0.35 tp c) tr= tp d) tr=3.5 tp
9.Lowpass RC circuit acts as integrator when_ [ ]
a)RC<<T b)RC>>T c)RC= =T d)RC<T
10.Q-factor of RLC parallel circuit is_ [ ]
a)Q=2K b)Q=3K c)Q=1/2K d)Q=1/3K
BLANKS:
11. If the input to LPRC circuit is exponential, the output is ___________________
12. Relation between rise time and Bandwidth of LP RC circuit is _______________________
13. A perfectly compensated attenuator is equivalent to a _____________________bridge
14. An RC integrator converts square wave into________________
15. To minimize distortion the time constant of a HPRC circuit must be ________ compared to pulse width.
TRUE / FALSE:
16. The current through an inductor cannot be made zero instantaneously [T/F]
17.The average valve of output voltage is zero for LP RC circuits [T/F]
18._across a capacitor cannot be reduced to zero instantaneously. [T/F]
19. Time constant of RC circuit is time required for output voltage to attain 50% of its steady state value. [T/F]
20. In the response of LPRC circuit to ramp input there is one time constant difference between input and output. [T/F]
UNIT - II
Multiple Choice Questions:
1. Two – level clipping is achieved by___________________ [ ]
a) Series clipper b) Shunt clipper c) Noise clipper d)double – ended clipper
2. Clipping circuit is also known as _________________ [ ]
a) slicer b) comparator c) clamping d) peaking circuit
3.In clampers the essential component is ____________________ [ ]
a) Resistor b) capacitor c) inductor d)None
4. The positive peaks of input are clamped to zero level. The type of clamper is ________ [ ]
a) Negative clamper b)Positive clamper c)Modified clamper d)synchronous clamper
5.Cutin voltage or Break point is a Ge diode is _____________________ [ ]
a) 0.6 V b) 0.2 V c) – 0 .5 V d) 0 .24 V
6.Clamping theorem is given by_ [ ]
a)Ar/Af=Rf/R b) Af / Ar=R/ Rf c) Ar/ Af=R/ Rf d) Af / Ar= Rf/R
7.A clipping circuit does not contain the following element. [ ]
a)resistor b)capacitor c)transistor d)junction diode
8.This condition refers to V0=Vi for Vi <VR+Vγ V0= VR+Vγ for Vi> VR+Vγ
a)series clipper below reference voltage [ ]
b)series clipper above reference voltage
c)shunt clipper above reference voltage
d)shunt clipper below reference voltage
9.The typical value of series resistance of a clipper is_ [ ]
a)R=RfRr b)R=√ RfRr c)R=Rf/ Rr d)R= Rf/ Rr
10.In emitter coupled clipper total input voltage swing ∆ Vi to carry the output is_ [ ]
a) ∆ Vi =ηVT /4.4 b) ∆ Vi =4.4 ηVT c) ∆ Vi= η /4.4 VT d) ∆ Vi=4.4/ ηVT
BLANKS:
11. Clipper uses __________________________ characteristics of diode & transistors
12. A sinusoidal wave is converted into trapezoidal wave by using ________________________ clipper
13. Clipping theorem is mathematically expressed as __________________________
14.The break point of junction diode depends on__________
15.Comparator make use of __________ nature of the output.
16.The cutin voltage Vγ for Si is____________
TRUE / FALSE:
17. Clipper circuit can be analyzed by output characteristics of transistor/diode [T/F]
18. In transistor clipper, the 1/P signal appear without distortion during its active region operation.[T/F]
19.The diode break point increases by about 2mv/oC with increase in temperature. [T/F]
20.Clipping circuit is a regenerative feedback comparator. [T/F]
UNIT - III
Multiple Choice Questions:
1. An ideal diode should have ____________________ [ ]
a) Zero forward resistance and Zero reverse resistance b) Zero R f & infinity Rr
c) Infinity R f & Zero Rr d) Infinity R f & infinity Rr
2. The time interval between application of base current and the start of collector current is [ ]
a) rise time b) delay time c)storage time d) fall time
3.In the Si transistor , typical valve of V be ( active ) at room temperature is ____ [ ]
a) 0 .3V b) 0. 7 V c) 0.6 V d) 0. 2V
4.The reverse saturation current is in the order of Ge diode _____________ [ ]
a) mA b) micro A c) n A d) Ampers
5.The switching of a transistor is characterized by __________________ [ ]
a) Cut off b)Saturation c) active d) cutoff and saturation
6.The reverse saturation current of a diode doubles for every [ ]
a)20 oC rise in temp. b)10oC rise in temp. c)15oC rise in temp d)40oC rise in temp.
7.In transistor cutoff region the biasing conditions are_ [ ]
a)EB junction forward biased&CB junction reverse biased
b)EB junction reverse biased&CB junction forward biased
c) EB junction forward biased& CB junction forward biased
d) EB junction reverse biased & CB junction reverse biased
8.ICBO for a Si transistor is in the order of_ [ ]
a)mA b)µA c)nA d)Ampere
9.The transistor is under saturation when [ ]
a)IB<IC/h FE b) IB<= IC/h FE c) IB> IC/h FE d) IB>= IC/h FE
10.VBE cutoff of Ge n-p-n transistor at 25oC is_ [ ]
a)0.1v b)0.3v c)0.2v d)-0.1v
BLANKS:
11. Increased width of collector junction transistor region results from increased collectorJunction voltage. This effect is called _______________________
12 The point of intersection of the load line with the breakdown Characteristics is called____________
13. The capacitance appears across reverse biased diode is called _____________________
14._____________is the reciprocal of slope of V-I characteristics.
15.power dissipation for Ge transistor is in the range of_____________
16.the transistor acts as open switch when it is in ________________region.
TRUE / FALSE:
17.Reverse saturation current diode for every 20 0 C rise in temperature in case of diode [T/F]
18. The mechanism due to early effect is called reach through [T/F]
19.the breakdown voltage of a transistor is due to avalanche breakdown. [T/F]
20.the time interval required to fall from 90% to 10% is delay time. [T/F]
UNIT - IV
Multiple Choice Questions:
1. A multivibrator Produces ________________ [ ]
a) Sine waves b) distorted sine waves c) square waves d) saw tooth voltages
2. A monostable multivibrator can be used to generate _______________ [ ]
a) pulse b) sweep c) sinusoids d) square
3.Which of the following circuit can be used convert a sine wave to a square wave ____ [ ]
a)A bistable multivibrator b) astable multivibretor c) schmitt trigger d) all of the above
4.which of the following does not require triggering __________________ [ ]
a)schmitt trigger b) Actable multivbrator c) Monostable multivbrator d) Bistable multivibrator
5.Unsymmetrical Triggering is adopted in following circuit _________________ [ ]
a) E mitter coupled binary b) Mono stable multi c) schmit trigger d) astable multi
6.Oneshot is alternate name of the following cicuit. [ ]
a)monostable multi b)bistable multi c)astable multi d)Schmitt trigger
7.The duration of time when conduction transfers from one transistor to other in bistable multi is_[ ]
a)decay time b)restoration time c)transition time d)setup time
8..The only circuit in which no triggering is required is_ [ ]
a)bistable b)monostable c)astable d)Schmitt trigger
9.The expression for time period of astable multi_ [ ]
a)t= 0.69RC b)t=1.38 RC c)t=1.44/(RA+RB)C d)RC
10.Schmitt trigger converts sine wave into [ ]
a)triangular b)sine c)square d)trapezoidal
BLANKS:
11. The capacitors which reduces the transition time incase of bistable multi are called ___________
12.Synmetrical triggering is also known as ______________________
13.Astable multi is referred as ____________________ to _____________________converter
14.Schmitt trigger is used as______________
15.___________triggering requires two triggering pulses from separate sources.
16.____________multivibrator can be used as a gating circuit.
TRUE / FALSE:
17.The voltage difference between UTP & LTP in case of Schmitt trigger is called Hysteresis voltage [T/F]
18.In symmetrical triggering , triggering signal induces the transition in only one direction [T/F]
19.Astable multi has one quasi stable state. [T/F]
20.Monostable multi is used to generate pulses. [T/F]
UNIT-V
1. The rate of change of ramp voltage with time is known as [ ]
a) Ramp speed b) clock speed c) differential speed d) sweep speed
2. Sweep speed error is give n by the formula [ ]
a) V s = ( e -T s / R C ) + 1 b) V s = V ( 1 + e -T s / R C )
c) V s = V ( 1 -e -T s / R C ) d) V s / V
3. The amplifier gain A should be in miller sweep circuit [ ]
a) infinity b ) 2 c ) z e r o d ) o n e
4. Sweep speed error is defined as [ ]
a) Initial ramp speed / final ramp speed b) Initial ramp speed - final ramp speed / initial ramp speed
c) Final ramp speed / initial ramp speed d) Initial ramp speed +final ramp speed /initial ramp speed
5. Sweep speed in a Boot strap Sweep circuit is given by [ ]
a) A v / RC b ) R c /A v c ) V / Rc d ) A i / c
6.The maximum deviation in rate of change of sweep voltage with time is called__________ [ ]
a)slope error b)transmission error c)sweep voltage d)none
7.Current time base generators are used in _ [ ]
a)radar b)sonar c)TV scanning d)where large raster area
8.The three different stages of ramp waveform are_ [ ]
a)RISE,fall,recycling b)recycling,non-return to zero c)recycling only
d)RISE or fall,recycling,return to zero
9.The following are basic building blocks of CRO’s &ADC [ ]
a)ramp generator b)yoke c)sweep generator d)square wave generator
10.The main drawback of sawtooth circuit is_ [ ]
a)moderate % of slope error b)overshoot error c)low% of slope error
d)high % of sweep speed error
BLANKS
11 .The difference between the input and output divided by the input is called a_________
12. Bootstrap sweep circuit employ s _____________________ feed back.
13.Time required for a sweep signal to return to original level is known as __________
14.The type of feedback in miller circuit is_
15.To improve the linearity in sweep circuit the technique is_
TRUE/FALSE
16. The circuit t that generates positive going Ramp is Miller’s sweep circuit. [T/F]
17. For a basic Boot strap integrator the transistor is connected as emitter follower. [T/F]
18.In miller sweep circuit the capacitor is grounded at one end. [T/F]
19.In current time base generator to correct linearity one should use squarewave. [T/F]
20.For TV sweep the overall power dissipation should be large. [T/F]
UNIT_VI
1. When two generators with equal frequencies run in synchronism the Synchronization
is said to be [ ]
a) one - to - on e basis b) one - to- many
c ) many to one d) multiplexing
2.In a Sinusoidal synchronization signal U J T is used as a switch because [ ]
a) Current divider b) negative resistance current cont rolled device
c) voltage divider d) negative resistance voltage cont rolled device
3. Synchronisation with frequency division is achieved in [ ]
( a) S weep circuit ( b ) Astable Multivibrator
( c ) Monostable Multi vibrator ( d ) Ramp generator
4. If synchronization is achieved with different frequencies, i e, one Frequency being twice the other then it is termed as [ ]
( a) frequency matching ( b ) synchronization ( c ) synchronization with frequency division
( d ) No synchronization occurs
5. Synchronization involves [ ]
( a) no change induced to switch on multivibrator ( b ) input & output are in phase
( c ) Input & output are out of phase ( d ) train of pulses that induce abrupt change in the state of multivibrator
6.By making _a divider circuit with a division factor can be built_ [ ]
a)T o=ηTp b) T o< ηTp c) T o> ηTp d) T o=2 ηTp
7.When two generators produce waveforms at different frequencies it is essential for proper synchronization that the frequency of one generator is _of the other generator. [ ]
a)secondary harmonics b)odd multiples c)even multiples d)integral multiple
8.synchronisation of sweep circuit can be obtained by_ [ ]
a)unsymmetrical signals b)identical phase signals c)non identical phase signals
d)symmetrical signals
9.stray signals are [ ]
a)does effect synchronization b)introduce distortion
c)affects synchronization severely d)unwanted noisy signals
BLANKS:
6. Monostable relaxation circuit is used as a____________________
7. The condition for proper transimission in a frequency division with out phase Jitter is given by___________
8. Synchronization of sweep circuit can be obtained by ___________
10.A _____________must be applied across an inductor to generate a ramp current.
11.The device used in relaxation oscillator is________________
12.One to one synchronization is achieved if the pulse amplitude must be_______________
TRUE/FALSE:
13. The condition for proper transmission in a frequency division with out phase Jitter is given by 2 T g < T p [T/F]
14. Phase jitter affect pulses of order nano sec [T/F]
15.Phase delay is independent of transistor characteristics. [T/F]
16.Phase jitter adversely effects large scale counters. [T/F]
17.For proper synchronization the sweep period should not effected by the synchronizing signal. [T/F]
UNIT-VII
1. When the sampling gate responds to the Signals of both polarities, it is termed as [ ]
( a) multidirectional gate ( b ) uni-directional gate ( c ) Non-directional gate ( d ) bi-directional gate
2. A sampling gate is also termed as [ ]
( a) non - linear gate ( b ) time - selection gate ( c ) time selection & linear gates ( d ) linear gat e
3. Sampling gate can not be used as a [ ]
(a) Sampling Scope ( b ) D t o A converter ( c ) Multiplexer ( d ) A t o D converter
4. The biggest disadvantage of sampling gate is [ ]
( a) the slow rise of control voltage ( b ) the slow rise of control current
( c ) Rise time fall time ( d ) fast rise of control voltage
5. Advantages of Diode sampling gate over the transistor sampling gat e are [ ]
( a) Linearity of operation and elimination of pedestal ( b ) stable operating point achievement
( c ) Linearity only ( d ) Non - linearity of operation and elimination of pedestal
6.The controlling digital signal is refered to as_ [ ]
a)gating signals b)trigger signal c)logic signal d)none
7.The control voltageVnmin in a bidirectional gate is_ [ ]
a)(RC/R2)*Vs b) (R2/ RC)*Vs c) RC/( R2*Vs) d)Vs R2 RC/4
8.The gain of bidirectional gate is [ ]
a)A=αRL/(RL+R3/2) b)A=α R3/(RL+R3/2) c)A= α2RL/(RL+R3) d)A= α2 R3/(RL+R3)
9.The deviation from linearity of 4-diode gate is _ [ ]
a)equal to 0.1% b)less than 0.1% c)greater than 0.1% d)none
10.The gating signal is also known as_(indicate false statement) [ ]
a)control pulse b)trigger pulse c)selector pulse d)enabling pulse
BLANKS
11. For an ideal switch the turn on and turn - off times are_____________
12. When the sampling gate responds to a single polarity it is termed as_______________
13. Chopper amplifier is also known as_______________________
14..For positive unidirectional signals,pedestal may be avoided by operating the transistor at__________
15.The ratio of Vo/Vs during the transmission interval is_
TRUE/FALSE
9. A transmission circuit which allows input signal to pass through it during selected interval and blocks its passage outside this time interval is called sampling gate [T/F]
10. The interval of time is selected by means of an externally applied signal is termed as sync pulse. [T/F]
18.Four diode gate requires one balanced voltage. [T/F]
19.A unidirectional gate which delivers an output pulse at coincidence of number of control voltages. [T/F]
20.We need n-p-n transistors for negative unidirectional signals.. [T/F]
UNIT_VIII
1. Typical Noise margin for a T T L family is given by [ ]
(a) 0 . 38V ( b ) 0 . 4 V ( c ) 0 . 10V ( d ) 0 . 42V
2. N O R operation is [ ]
( a) ¯ X . ¯ Y ( b ) ¯ X + ¯ Y ( c ) ( ¯ X + ¯ Y ) ( ¯ X + ¯ Y ) ( d ) X Y
3. The I C 74 02 refers to — — — — — — – [ ]
( a) N O R ( b ) N A N D ( c ) X N O R ( d ) XOR
4. The Bipolar technology giving the fastest logical family is [ ]
( a) E C L ( b ) RT L ( c ) D T L ( d ) T T L
5. A N A N D gate is called as universal logic element because [ ]
( a) N O R gate alone
( b ) any logic function can be realized by N A N D gate alone
( c ) all the minimizing techniques are applicable for optimum N A N D gate realization
( d ) many digital computers use N A N D gates
6.Fan-out for DTL is_ [ ]
a)large b)small c)medium d)very small
7.Most computers using pulses operate as_ [ ]
a)dynamic logic system b)d.c logic system c)d.c negative logic system
d)sychronisation system
8.The logic family in which no resistors ,diodes used between stages is_ [ ]
a)TTL b)DCTL c)ECL d)DTL
9.what are the universal gates, [ ]
a)AND,OR b)NOT,AND c)NAND,NOR d)NOR,NAND
10.The circuit which uses multi emitter transistor is_ [ ]
a)DTL b)TTL c)both d)none
BLANKS
11. Allowed Fan - out for Low power T T L is ____________________
12. Power dissipation per gat e in milli watts for CMOS logic family is______________
13. High noise margin is achievable in ______________logic families.
14.In ____________system a number is represented in serial form by a train of pulses.
15.A positive logic AND gate uses______________for shunting the output.
TRUE/FALSE
16.A negation following an OR is called EX-OR gate. [T/F]
17.A TTL gate is capable of high speed at low power levels. [T/F]
18.The speed of gate is characterized by propogation time delay. [T/F]
19. Totem-pole output TTL provides less propagation delay compared to open collector TTL. [T/F]
20. The low power dissipation is in N M O S technology. [T/F]